JPS55160341A - Preventing circuit for error erasure of auto reverse unit - Google Patents

Preventing circuit for error erasure of auto reverse unit

Info

Publication number
JPS55160341A
JPS55160341A JP6804079A JP6804079A JPS55160341A JP S55160341 A JPS55160341 A JP S55160341A JP 6804079 A JP6804079 A JP 6804079A JP 6804079 A JP6804079 A JP 6804079A JP S55160341 A JPS55160341 A JP S55160341A
Authority
JP
Japan
Prior art keywords
recording
tape
circuit
reproducing
track
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6804079A
Other languages
Japanese (ja)
Inventor
Teruo Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6804079A priority Critical patent/JPS55160341A/en
Publication of JPS55160341A publication Critical patent/JPS55160341A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent recorded contents from being erased when a tape traveling direction is inverted, by delaying the operation of a bias oscillating circuit accompanying the switching of a recording/reproducing switch.
CONSTITUTION: While recording contents of one track on tape 44 are reproduced, contact 25 of recording/reproducing switch 23 is opened and bias oscillating circuit 31 is inoperative. Then, when the traveling direction of tape 44 is inverted to start recording on the other track, contact 25 of switch 23 is made and after complete change-over control over a recording/reproducing head connected to terminal 34 to the other track side of tape 44, an increase in the output voltage of circuit 31 is delayed until capacitor C3 is charged via resistance R2. After C3 is charged, the output of circuit 31 is supplied to the recording/reproducing head and erasing head 42.
COPYRIGHT: (C)1980,JPO&Japio
JP6804079A 1979-05-31 1979-05-31 Preventing circuit for error erasure of auto reverse unit Pending JPS55160341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6804079A JPS55160341A (en) 1979-05-31 1979-05-31 Preventing circuit for error erasure of auto reverse unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6804079A JPS55160341A (en) 1979-05-31 1979-05-31 Preventing circuit for error erasure of auto reverse unit

Publications (1)

Publication Number Publication Date
JPS55160341A true JPS55160341A (en) 1980-12-13

Family

ID=13362281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6804079A Pending JPS55160341A (en) 1979-05-31 1979-05-31 Preventing circuit for error erasure of auto reverse unit

Country Status (1)

Country Link
JP (1) JPS55160341A (en)

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