JPS55157018A - Digital control unit - Google Patents

Digital control unit

Info

Publication number
JPS55157018A
JPS55157018A JP6390879A JP6390879A JPS55157018A JP S55157018 A JPS55157018 A JP S55157018A JP 6390879 A JP6390879 A JP 6390879A JP 6390879 A JP6390879 A JP 6390879A JP S55157018 A JPS55157018 A JP S55157018A
Authority
JP
Japan
Prior art keywords
terminal
input
circuit
signal
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6390879A
Other languages
Japanese (ja)
Inventor
Hiroshi Ozaki
Kimiya Nishimae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6390879A priority Critical patent/JPS55157018A/en
Publication of JPS55157018A publication Critical patent/JPS55157018A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an expected value from standard units and to increase the efficiency of function inspection, by providing terminals and circuits for comparison inspection.
CONSTITUTION: The output of an oscillation circuit 2 provided at a wiring board 1 is input to FF circuits F1WF3 forming clock pulses to form internal clock signals ϕ13. A circuit G is provided with a terminal P2 inputting pulse signals. Further, a terminal P1 receiving the control input signal from the circuit G is provided. Thus, the control input closes the circuit G to inhibit the transmission of oscillation output and the pulse signal from an inspection unit is fed from the terminal P2. Further, the gate circuit in a control unit as a standard product is similarly controlled and the pulse signal from the insepction unit is input to the terminal P2. Moreover, a reset input terminal P3 of the FF circuits F1WF3 is provided, and when a reset signal is input to the terminal from an inspection unit commonly, the phase of clock signal between inspected product and the standard product can be made in agreement.
COPYRIGHT: (C)1980,JPO&Japio
JP6390879A 1979-05-25 1979-05-25 Digital control unit Pending JPS55157018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6390879A JPS55157018A (en) 1979-05-25 1979-05-25 Digital control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6390879A JPS55157018A (en) 1979-05-25 1979-05-25 Digital control unit

Publications (1)

Publication Number Publication Date
JPS55157018A true JPS55157018A (en) 1980-12-06

Family

ID=13242891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6390879A Pending JPS55157018A (en) 1979-05-25 1979-05-25 Digital control unit

Country Status (1)

Country Link
JP (1) JPS55157018A (en)

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