JPS5590885A - Alarm clock with snooze - Google Patents

Alarm clock with snooze

Info

Publication number
JPS5590885A
JPS5590885A JP16592578A JP16592578A JPS5590885A JP S5590885 A JPS5590885 A JP S5590885A JP 16592578 A JP16592578 A JP 16592578A JP 16592578 A JP16592578 A JP 16592578A JP S5590885 A JPS5590885 A JP S5590885A
Authority
JP
Japan
Prior art keywords
snooze
circuit
circuit portion
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16592578A
Other languages
Japanese (ja)
Inventor
Hiroshi Itoyama
Minoru Kuroda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP16592578A priority Critical patent/JPS5590885A/en
Publication of JPS5590885A publication Critical patent/JPS5590885A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electromechanical Clocks (AREA)

Abstract

PURPOSE: To make it possible to form a snooze circuit portion of an alarm clock with LSI just as a clock circuit portion thereof, by forming the snooze circuit with an electronic circuit only.
CONSTITUTION: One output from a flip-flop 10 is applied to integrating circuits RT, CT through a Schumit trigger 11, and outputs from these integrating circuits are input into a terminal R of the flip-flop 10. When a touch switch 7 is operated, a terminal F of the flip-flop 10 is kept at H-level for a predetermined period of time owing to the above-mentioned circuits, and a signal of this level is applied to an output control portion 5 of an alarm. As a result, the generation of an alarm sound is suppressed for a predetermined period of time even a reference switch 4 is turned on. Thus, a snooze circuit can be formed with an electronic circuit only. Consequently, the snooze circuit portion can be formed with an electronic circuit only just as a clock circuit portion, with only a small number of parts, such as capacitors added externally to the snooze circuit portion.
COPYRIGHT: (C)1980,JPO&Japio
JP16592578A 1978-12-29 1978-12-29 Alarm clock with snooze Pending JPS5590885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16592578A JPS5590885A (en) 1978-12-29 1978-12-29 Alarm clock with snooze

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16592578A JPS5590885A (en) 1978-12-29 1978-12-29 Alarm clock with snooze

Publications (1)

Publication Number Publication Date
JPS5590885A true JPS5590885A (en) 1980-07-09

Family

ID=15821607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16592578A Pending JPS5590885A (en) 1978-12-29 1978-12-29 Alarm clock with snooze

Country Status (1)

Country Link
JP (1) JPS5590885A (en)

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