JPS55156333A - Si chip replacing method - Google Patents

Si chip replacing method

Info

Publication number
JPS55156333A
JPS55156333A JP6382579A JP6382579A JPS55156333A JP S55156333 A JPS55156333 A JP S55156333A JP 6382579 A JP6382579 A JP 6382579A JP 6382579 A JP6382579 A JP 6382579A JP S55156333 A JPS55156333 A JP S55156333A
Authority
JP
Japan
Prior art keywords
chips
chip
container
heater
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6382579A
Other languages
Japanese (ja)
Inventor
Tasao Soga
Kazuya Takahashi
Akihiro Kenmochi
Munenobu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6382579A priority Critical patent/JPS55156333A/en
Publication of JPS55156333A publication Critical patent/JPS55156333A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/799—Apparatus for disconnecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To stabilize the conditions for replacing chips by a method wherein a space is formed under the substrate and the substrate is carried on the insulator when removing or attaching the Si chips from or to the ceramic substrate. CONSTITUTION:A heater 14 is disposed within a tefron container 13, a net 15 is covered above the heater 14 with a space and air is introduced from the side wall of the bottom of the container 13 thereinto. On the opened upper end of thus arranged container 13, a ceramic substrate 8 having a heat sink 10 is placed at its rear side, on which a plurality of Si chips 3 are located through solders 4. The Si chips are covered with an Al shield plate 7 while exposing only a chip 3 to be removed from or attched to and an infrared lamp 1 including a reflecting mirror 2 is disposed thereabove, so that the chip 3 is heated from both upper and lower sides and then the solders 4 are melted. At this time, the chip 3 is handled by means of an Si chip suction pipe 6 having a coil heater 5 wound round the same. By so doing, works for removing or attaching the Si chips is significantly stabilized.
JP6382579A 1979-05-25 1979-05-25 Si chip replacing method Pending JPS55156333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6382579A JPS55156333A (en) 1979-05-25 1979-05-25 Si chip replacing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6382579A JPS55156333A (en) 1979-05-25 1979-05-25 Si chip replacing method

Publications (1)

Publication Number Publication Date
JPS55156333A true JPS55156333A (en) 1980-12-05

Family

ID=13240521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6382579A Pending JPS55156333A (en) 1979-05-25 1979-05-25 Si chip replacing method

Country Status (1)

Country Link
JP (1) JPS55156333A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391501A (en) * 1992-11-12 1995-02-21 Hitachi, Ltd. Method for manufacturing integrated circuits with a step for replacing defective circuit elements
JP2007180458A (en) * 2005-12-28 2007-07-12 Toyota Industries Corp Soldering method, method of manufacturing semiconductor module, and soldering apparatus
JP2008524814A (en) * 2004-12-20 2008-07-10 アーベーベー・リサーチ・リミテッド Vacuum circuit breaker with high current carrying capacity
EP3373325A4 (en) * 2015-11-05 2019-05-01 Furukawa Electric Co. Ltd. Die bonding device and die bonding method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391501A (en) * 1992-11-12 1995-02-21 Hitachi, Ltd. Method for manufacturing integrated circuits with a step for replacing defective circuit elements
JP2008524814A (en) * 2004-12-20 2008-07-10 アーベーベー・リサーチ・リミテッド Vacuum circuit breaker with high current carrying capacity
JP2007180458A (en) * 2005-12-28 2007-07-12 Toyota Industries Corp Soldering method, method of manufacturing semiconductor module, and soldering apparatus
JP4640170B2 (en) * 2005-12-28 2011-03-02 株式会社豊田自動織機 Soldering method, semiconductor module manufacturing method, and soldering apparatus
EP3373325A4 (en) * 2015-11-05 2019-05-01 Furukawa Electric Co. Ltd. Die bonding device and die bonding method

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