JPS55149529A - Electronic circuit - Google Patents

Electronic circuit

Info

Publication number
JPS55149529A
JPS55149529A JP5659779A JP5659779A JPS55149529A JP S55149529 A JPS55149529 A JP S55149529A JP 5659779 A JP5659779 A JP 5659779A JP 5659779 A JP5659779 A JP 5659779A JP S55149529 A JPS55149529 A JP S55149529A
Authority
JP
Japan
Prior art keywords
signal
input
sample
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5659779A
Other languages
Japanese (ja)
Inventor
Chiaki Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5659779A priority Critical patent/JPS55149529A/en
Publication of JPS55149529A publication Critical patent/JPS55149529A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier

Landscapes

  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To hold the peak value of input signal pulse even to the input signal lower in the stability of repetitive frequency, by producing the sample signal from the input signal pulse itself and by the sample hold. CONSTITUTION:The signal 8 input from the signal input terminal 1 is input to the delay circuit 2 and the comparator 3. The output 10 of the comparator 3 and the prediction gate signal 11 from the prediction gate signal input terminal 4 are input to the AND circuit 5 and the sample signal 12 eliminating excessive pulses can be obtained. The delay circuit 2 is a circuit to compensate the difference between the leading time of the signal 8 and that of the sample signal 12. Accordingly, the signal 9 after passing through the delay circuit 2 is always in synchronizing with the sample signal 12, it is sample-held at the sample hold circuit 6 and it is output from the output terminal 7 as the stable output signal waveform 13.
JP5659779A 1979-05-09 1979-05-09 Electronic circuit Pending JPS55149529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5659779A JPS55149529A (en) 1979-05-09 1979-05-09 Electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5659779A JPS55149529A (en) 1979-05-09 1979-05-09 Electronic circuit

Publications (1)

Publication Number Publication Date
JPS55149529A true JPS55149529A (en) 1980-11-20

Family

ID=13031605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5659779A Pending JPS55149529A (en) 1979-05-09 1979-05-09 Electronic circuit

Country Status (1)

Country Link
JP (1) JPS55149529A (en)

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