JPS5514742A - Circuit multiplication system - Google Patents

Circuit multiplication system

Info

Publication number
JPS5514742A
JPS5514742A JP8737478A JP8737478A JPS5514742A JP S5514742 A JPS5514742 A JP S5514742A JP 8737478 A JP8737478 A JP 8737478A JP 8737478 A JP8737478 A JP 8737478A JP S5514742 A JPS5514742 A JP S5514742A
Authority
JP
Japan
Prior art keywords
circuit
frame synchronous
low
speed
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8737478A
Other languages
Japanese (ja)
Inventor
Masami Sengoku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8737478A priority Critical patent/JPS5514742A/en
Publication of JPS5514742A publication Critical patent/JPS5514742A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To increase the transmission efficiency by transmitting the frame synchronous pattern only when no transmission data exists and then transmitting the low-speed circuit via the frame synchronous pattern insertion time slot. CONSTITUTION:Low-speed circuits 370-373 stored into multiplying device TDM via transmission buffer FIFO are connected to high-speed circuit HW via signal distributor SCN and circuit connection unit MDM. And each circuit data is made to oppose to CH1-CH4 within frame 400 of HW. In case no data exists at low-speed circuit 370, the time slot of CH1 within HWis changed into frame synchronous pattern F. This pattern is then checked through frame synchronous check circuit FCK.
JP8737478A 1978-07-17 1978-07-17 Circuit multiplication system Pending JPS5514742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8737478A JPS5514742A (en) 1978-07-17 1978-07-17 Circuit multiplication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8737478A JPS5514742A (en) 1978-07-17 1978-07-17 Circuit multiplication system

Publications (1)

Publication Number Publication Date
JPS5514742A true JPS5514742A (en) 1980-02-01

Family

ID=13913113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8737478A Pending JPS5514742A (en) 1978-07-17 1978-07-17 Circuit multiplication system

Country Status (1)

Country Link
JP (1) JPS5514742A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6326046A (en) * 1986-07-18 1988-02-03 Nec Corp Tdm frame synchronism establishment system
FR2644659A1 (en) * 1989-03-20 1990-09-21 France Etat IMPROVED END PROCESS AND EQUIPMENT FOR ESTABLISHING HIGH THROUGHPUT TELECOMMUNICATIONS LINKS THROUGH INDEPENDENT CHANNELS
US6137795A (en) * 1997-03-19 2000-10-24 Fujitsu Limited Cell switching method and cell exchange system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6326046A (en) * 1986-07-18 1988-02-03 Nec Corp Tdm frame synchronism establishment system
FR2644659A1 (en) * 1989-03-20 1990-09-21 France Etat IMPROVED END PROCESS AND EQUIPMENT FOR ESTABLISHING HIGH THROUGHPUT TELECOMMUNICATIONS LINKS THROUGH INDEPENDENT CHANNELS
US6137795A (en) * 1997-03-19 2000-10-24 Fujitsu Limited Cell switching method and cell exchange system

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