JPS55145353A - Fabricating method of semiconductor chip - Google Patents
Fabricating method of semiconductor chipInfo
- Publication number
- JPS55145353A JPS55145353A JP5237879A JP5237879A JPS55145353A JP S55145353 A JPS55145353 A JP S55145353A JP 5237879 A JP5237879 A JP 5237879A JP 5237879 A JP5237879 A JP 5237879A JP S55145353 A JPS55145353 A JP S55145353A
- Authority
- JP
- Japan
- Prior art keywords
- chips
- recesses
- divided
- wax
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
PURPOSE:To fully automate the fabrication of a diode chip or the like by containing and conveying divided semiconductor chips while regularly aligning the chips to eliminate the necessity of checking or realigning the aigned chips by a manual work. CONSTITUTION:A semiconductor wafer 1 to be divided into a plurality of chips is so adhered to a retainer jig 2 of transparent member having recesses 2a-2c responsive to the number of chips through wax 3 that the chip regions face oppositely the recesses 2a-2c, respectively. Then, the wafer 1 on the jig 2 is divided into independent chips 1a-1f, the wax 3 is dissolved and removed by solvent in adhered state, and the chips 1a-1f are accommodated in the recesses 2a-2c, respectively of the tool 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54052378A JPS5929152B2 (en) | 1979-04-27 | 1979-04-27 | Method of manufacturing semiconductor chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54052378A JPS5929152B2 (en) | 1979-04-27 | 1979-04-27 | Method of manufacturing semiconductor chips |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55145353A true JPS55145353A (en) | 1980-11-12 |
JPS5929152B2 JPS5929152B2 (en) | 1984-07-18 |
Family
ID=12913132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54052378A Expired JPS5929152B2 (en) | 1979-04-27 | 1979-04-27 | Method of manufacturing semiconductor chips |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5929152B2 (en) |
-
1979
- 1979-04-27 JP JP54052378A patent/JPS5929152B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5929152B2 (en) | 1984-07-18 |
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