JPS55141988A - Motor speed controlling circuit - Google Patents
Motor speed controlling circuitInfo
- Publication number
- JPS55141988A JPS55141988A JP4671679A JP4671679A JPS55141988A JP S55141988 A JPS55141988 A JP S55141988A JP 4671679 A JP4671679 A JP 4671679A JP 4671679 A JP4671679 A JP 4671679A JP S55141988 A JPS55141988 A JP S55141988A
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- signal
- phase
- counter
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/22—Controlling the speed digitally using a reference oscillator, a speed proportional pulse rate feedback and a digital comparator
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Electric Motors In General (AREA)
Abstract
PURPOSE:To simplify the constitution from avoiding a necessity of low-pass filter by a method wherein a pulse signal is counted according to a difference in phase between a detected pulse signal and a reference pulse signal, and a motor is contolled for speed according to the counted value and phase leading/lagging information. CONSTITUTION:In case a phase of a detected pulse signal S2 lags from a reference pulse signal S1, a signal Sa becomes ''1'' from the reference pulse signal S1 being inputted, and a counter 17 keeps to count a pulse signal S0 until the detected pulse signal S2 is inputted. In case, however, the phase of the detected pulse signal S2 is ''0'' while the counter 17 counts the pulse signal S0. A read-only memory 18 gives binary code signals D1-D7 according to an output signal of the counter 17 and a sign bit D0 according to the signal Sa to a motor 1 through D/A converter 19.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4671679A JPS55141988A (en) | 1979-04-18 | 1979-04-18 | Motor speed controlling circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4671679A JPS55141988A (en) | 1979-04-18 | 1979-04-18 | Motor speed controlling circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55141988A true JPS55141988A (en) | 1980-11-06 |
Family
ID=12755063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4671679A Pending JPS55141988A (en) | 1979-04-18 | 1979-04-18 | Motor speed controlling circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55141988A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59103598U (en) * | 1982-09-11 | 1984-07-12 | 古野電気株式会社 | DC motor drive circuit |
-
1979
- 1979-04-18 JP JP4671679A patent/JPS55141988A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59103598U (en) * | 1982-09-11 | 1984-07-12 | 古野電気株式会社 | DC motor drive circuit |
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