JPS55140366A - Fault detecting system in facsimile - Google Patents
Fault detecting system in facsimileInfo
- Publication number
- JPS55140366A JPS55140366A JP4787079A JP4787079A JPS55140366A JP S55140366 A JPS55140366 A JP S55140366A JP 4787079 A JP4787079 A JP 4787079A JP 4787079 A JP4787079 A JP 4787079A JP S55140366 A JPS55140366 A JP S55140366A
- Authority
- JP
- Japan
- Prior art keywords
- timer circuit
- line connection
- overflow
- fault
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
- H04N1/32609—Fault detection or counter-measures, e.g. original mis-positioned, shortage of paper
- H04N1/32614—Fault detection or counter-measures, e.g. original mis-positioned, shortage of paper related to a single-mode communication, e.g. at the transmitter or at the receiver
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimiles In General (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
PURPOSE:To make it possible to detect and cope with the fault of CPU system control facsimile properly, by providing a timer circuit and by controlling the timer circuit so that the timer circuit may generate the overflow output at a fault time. CONSTITUTION:In case that the CPU executes the porcessing program normally, timer circuit 4 does not generate overflow. When the CPU becomes abnormal, the control is returned to the fault detection step to repeat the same step in the processing program, and the control cannot escape from this state. Then, the reset instruction of the timer is not executed within a prescribed time, and FF2 is reset still by the clock signal from the MODEM, and monostable multivibrator 3 is not triggerred, and then, circuit 4 generates the overflow signal to set FF5, and AND gate 6 is closed. Consequently, the line connection signal transmitted to the network control unit is inhibited. In case of anomaly occurrence in line connection, troubles such as line disconnection and unnecessarily long line connection can be avoided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4787079A JPS55140366A (en) | 1979-04-20 | 1979-04-20 | Fault detecting system in facsimile |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4787079A JPS55140366A (en) | 1979-04-20 | 1979-04-20 | Fault detecting system in facsimile |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55140366A true JPS55140366A (en) | 1980-11-01 |
JPS62623B2 JPS62623B2 (en) | 1987-01-08 |
Family
ID=12787402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4787079A Granted JPS55140366A (en) | 1979-04-20 | 1979-04-20 | Fault detecting system in facsimile |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55140366A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63181848A (en) * | 1987-01-23 | 1988-07-27 | 昭和電工建材株式会社 | Construction method for clamping outer wall panel |
-
1979
- 1979-04-20 JP JP4787079A patent/JPS55140366A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62623B2 (en) | 1987-01-08 |
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