JPS55138144A - Data write system of crt display unit - Google Patents

Data write system of crt display unit

Info

Publication number
JPS55138144A
JPS55138144A JP4557279A JP4557279A JPS55138144A JP S55138144 A JPS55138144 A JP S55138144A JP 4557279 A JP4557279 A JP 4557279A JP 4557279 A JP4557279 A JP 4557279A JP S55138144 A JPS55138144 A JP S55138144A
Authority
JP
Japan
Prior art keywords
write
las
selector
address
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4557279A
Other languages
Japanese (ja)
Inventor
Masayuki Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4557279A priority Critical patent/JPS55138144A/en
Publication of JPS55138144A publication Critical patent/JPS55138144A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the generation of noises by simplifying circuit constitution while increasing a write speed by sending a write signal to a memory stroed with data of characters to be displayed in rasters while a beam scans a cursor blank part.
CONSTITUTION: Dot clock pulse DCP is applied to free-running address counter SAC and the output of line counter C4 is applied to line address selector LAS, which is further applied with write line address WLA. Then, outputs FCC0WFCC5 of column counter C2 are applied to coincidence circuit CIC, which is also applied with write solumn address WCA at the other input, and the output of selector LAS and circuit CIC and AND-ed by AND gate G2. Screen memory SCM is stored with data corresponding to characters in a block and while a beam scans a cursor blank part, write signal MWR is supplied from gate G2 to this memory SCM; and outputs VA3, VA0 are supplied from selector LAS to increase a write speed.
COPYRIGHT: (C)1980,JPO&Japio
JP4557279A 1979-04-13 1979-04-13 Data write system of crt display unit Pending JPS55138144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4557279A JPS55138144A (en) 1979-04-13 1979-04-13 Data write system of crt display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4557279A JPS55138144A (en) 1979-04-13 1979-04-13 Data write system of crt display unit

Publications (1)

Publication Number Publication Date
JPS55138144A true JPS55138144A (en) 1980-10-28

Family

ID=12723053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4557279A Pending JPS55138144A (en) 1979-04-13 1979-04-13 Data write system of crt display unit

Country Status (1)

Country Link
JP (1) JPS55138144A (en)

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