JPS55137780A - Receiving processing method of facsimile communication control frame - Google Patents

Receiving processing method of facsimile communication control frame

Info

Publication number
JPS55137780A
JPS55137780A JP4621279A JP4621279A JPS55137780A JP S55137780 A JPS55137780 A JP S55137780A JP 4621279 A JP4621279 A JP 4621279A JP 4621279 A JP4621279 A JP 4621279A JP S55137780 A JPS55137780 A JP S55137780A
Authority
JP
Japan
Prior art keywords
flag
dec1
pattern
information
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4621279A
Other languages
Japanese (ja)
Inventor
Mitsuru Kaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP4621279A priority Critical patent/JPS55137780A/en
Publication of JPS55137780A publication Critical patent/JPS55137780A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/00095—Systems or arrangements for the transmission of the picture signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Transmission Control (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To make it possible to detect pattern information and information other than pattern information by reading and deciding a specific code of receiving data. CONSTITUTION:Receiving data is inputted to shift register SR1 and is outputted to decoder DEC1, and there, a flag detection signal is generated when flag pattern 01111110 is detected, and a zero elimination signal is generated when 0 following 5 continuous 1's other than the flag pattern is detected. If the flag detection signal of DEC1 is not issued when counter COU1 generates an overflow pulse by the 8-pulse receiving clock, information in the frame following the flag is received. When DEC1 generates the zero elimination signal, clocks are stopped by AND gate AN4. By this clock, data is shifted and inputted to shift register SR3 and is outputted to buffer BF1. BF1 is set to output a buffer full signal. When the flag pattern indicating the end of the frame is inputted to SR1, the flag detection signal is generated from DEC1 to reset FF3. Thus, receiving of one frame terminates.
JP4621279A 1979-04-16 1979-04-16 Receiving processing method of facsimile communication control frame Pending JPS55137780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4621279A JPS55137780A (en) 1979-04-16 1979-04-16 Receiving processing method of facsimile communication control frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4621279A JPS55137780A (en) 1979-04-16 1979-04-16 Receiving processing method of facsimile communication control frame

Publications (1)

Publication Number Publication Date
JPS55137780A true JPS55137780A (en) 1980-10-27

Family

ID=12740782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4621279A Pending JPS55137780A (en) 1979-04-16 1979-04-16 Receiving processing method of facsimile communication control frame

Country Status (1)

Country Link
JP (1) JPS55137780A (en)

Similar Documents

Publication Publication Date Title
JPS57204977A (en) Method and device for bar code read
JPS55137780A (en) Receiving processing method of facsimile communication control frame
FR2678122B1 (en) DEVICE FOR MEASURING THE FLOW OF VIRTUAL CIRCUITS EMPLOYING AN ASYNCHRONOUS MULTIPLEXED COMMUNICATION CHANNEL.
ES8405174A1 (en) A timing control system in a data processor.
JPS56114071A (en) Arithmetic circuit
JPS54107717A (en) Counting display system
JPS5411708A (en) Peak detecting system
CA2021744A1 (en) Fast maximum likelihood decoder
JPS537272A (en) Electronic timepiece
JPS567180A (en) Character recognizing method for optical character reader
JPS5752815A (en) Processing circuit for ultrasonic wave signal
KR960003182A (en) Line Redundancy Unit in HDLC NRZI Communication System
JPS57132478A (en) Decoding system for variable length code
JPS57141176A (en) Detection system for synchronizing signal in facsimile signal
JPS5769957A (en) Pattern detection circuit
KR100435560B1 (en) Method for receiving differential code in micom, especially data inputted into int1 and int2 is separated
JPS6454307A (en) Rotating speed detector
JPS54162526A (en) Vertical synchronizing detection system in pcm system recorder-reproducer
JPS5710571A (en) Photoelectric hybrid type interpolation processor
JPS5798170A (en) Discriminating track reading system
JPS647373A (en) Digital recording control mechanism
ATE129808T1 (en) METHOD AND DEVICE FOR DETERMINING CONSUMPTION.
JPS6451829A (en) Data processing method in rds receiver
JPS57189315A (en) Signal detecting circuit
JPS5798038A (en) Decoding system for code