JPS55132598A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS55132598A
JPS55132598A JP3773179A JP3773179A JPS55132598A JP S55132598 A JPS55132598 A JP S55132598A JP 3773179 A JP3773179 A JP 3773179A JP 3773179 A JP3773179 A JP 3773179A JP S55132598 A JPS55132598 A JP S55132598A
Authority
JP
Japan
Prior art keywords
signal
time
terminal
delay
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3773179A
Other languages
Japanese (ja)
Other versions
JPS616478B2 (en
Inventor
Satoru Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kawai Musical Instrument Manufacturing Co Ltd
Original Assignee
Kawai Musical Instrument Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawai Musical Instrument Manufacturing Co Ltd filed Critical Kawai Musical Instrument Manufacturing Co Ltd
Priority to JP3773179A priority Critical patent/JPS55132598A/en
Publication of JPS55132598A publication Critical patent/JPS55132598A/en
Publication of JPS616478B2 publication Critical patent/JPS616478B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE: To enable to store the signal for considerably long time, by inserting the gate to the input side of the signal delay element and the feedback circuit respectively for switching control.
CONSTITUTION: When the signal A is fed to the terminal Ti from the time tO, gate G1 is open and when G2 is closed, the signal A is fed to the delay element L. Further, when the time t1 reaches through the delay time t1, the signal B is outputted to the terminal TO. At this time, G2 is open and G1 is closed, then the signal B is inputted again to the element L via the feedback circuit F. Further, after the delay time TL, the signal C is obtained at the terminal TO again. Accordingly, the signal can be stored.
COPYRIGHT: (C)1980,JPO&Japio
JP3773179A 1979-03-31 1979-03-31 Memory unit Granted JPS55132598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3773179A JPS55132598A (en) 1979-03-31 1979-03-31 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3773179A JPS55132598A (en) 1979-03-31 1979-03-31 Memory unit

Publications (2)

Publication Number Publication Date
JPS55132598A true JPS55132598A (en) 1980-10-15
JPS616478B2 JPS616478B2 (en) 1986-02-26

Family

ID=12505629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3773179A Granted JPS55132598A (en) 1979-03-31 1979-03-31 Memory unit

Country Status (1)

Country Link
JP (1) JPS55132598A (en)

Also Published As

Publication number Publication date
JPS616478B2 (en) 1986-02-26

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