JPS55125726A - Exclusive logical sum circuit - Google Patents

Exclusive logical sum circuit

Info

Publication number
JPS55125726A
JPS55125726A JP3296179A JP3296179A JPS55125726A JP S55125726 A JPS55125726 A JP S55125726A JP 3296179 A JP3296179 A JP 3296179A JP 3296179 A JP3296179 A JP 3296179A JP S55125726 A JPS55125726 A JP S55125726A
Authority
JP
Japan
Prior art keywords
resistor
terminal
potential
diodes
inverting input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3296179A
Other languages
Japanese (ja)
Other versions
JPS6113414B2 (en
Inventor
Masaki Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP3296179A priority Critical patent/JPS55125726A/en
Publication of JPS55125726A publication Critical patent/JPS55125726A/en
Publication of JPS6113414B2 publication Critical patent/JPS6113414B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain the circuit enabling the exclusive logical sum operation to the signal of positive and negative polarities, by constituting four diodes, one operational amplifier and three input resistors in series connection. CONSTITUTION:When the terminal IN1 and IN2 are both of negative potential, current flows from zero potential to the terminal IN1 through the diodes D1, D2 and resistor R1, and the current of the diode D1 and resistor R2, and the current of diodes D1, D2, D3 and resistor R3 flow to the terminal IN2, then the potential of non-inverting input terminal of the operational amplifier OA is higher than the potential of the non-inverting input terminal and the output of the amplifier OAis of negative potential. When the terminal N1 is positive and terminal IN2 is negative potential, current flows from the terminal IN1 to IN2 through the resistor R1, diode D3 and resistor R3. Further, current flows from IN1 to resistor R1, and diodes D3 and D4. When the resistor is selected so that the current flowing to the resistor R1 and diode D3 is greater than the current flowing to the resistor R3, the non- inverting input portential of the amplifier OA is higher than the inverting input potential, and the output signal is at positive potential. The turth table listed is obtained with similar method.
JP3296179A 1979-03-20 1979-03-20 Exclusive logical sum circuit Granted JPS55125726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3296179A JPS55125726A (en) 1979-03-20 1979-03-20 Exclusive logical sum circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3296179A JPS55125726A (en) 1979-03-20 1979-03-20 Exclusive logical sum circuit

Publications (2)

Publication Number Publication Date
JPS55125726A true JPS55125726A (en) 1980-09-27
JPS6113414B2 JPS6113414B2 (en) 1986-04-14

Family

ID=12373508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3296179A Granted JPS55125726A (en) 1979-03-20 1979-03-20 Exclusive logical sum circuit

Country Status (1)

Country Link
JP (1) JPS55125726A (en)

Also Published As

Publication number Publication date
JPS6113414B2 (en) 1986-04-14

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