JPS55123256A - Synchronous detection system - Google Patents
Synchronous detection systemInfo
- Publication number
- JPS55123256A JPS55123256A JP3022579A JP3022579A JPS55123256A JP S55123256 A JPS55123256 A JP S55123256A JP 3022579 A JP3022579 A JP 3022579A JP 3022579 A JP3022579 A JP 3022579A JP S55123256 A JPS55123256 A JP S55123256A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- state
- abnormal state
- synchronous
- changes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Abstract
PURPOSE:To make it possible to detect rapidly an abnormal state without deteriorating the data processing performance of a communication controller and also to perform cutting operation in a short time by providing a circuit which detects the abnormal state in parallel to synchronous test operation. CONSTITUTION:When the state of receiving circuit R changes from ''1'' to ''0'' at time t0 and the state of indication circuit I also changes from OFF to ON, an abnormal state of circuit cutting indication is considered to have occurred. Then, this state is immediately detected to change the state of control circuit C from ON to OFF, and the state of transmitting circuit T is also changed from ''1'' to ''0'' to complete response operation (t1-t0) of incoming disconnection in a short time (within 100ms). Namely, before a synchronous character or start flag is tested by synchronous test circuit 27, the generation of eight continuous bits of ''0'' is detected by ''0'' detection circuit 28 to send interruption signal INT to a main control part and a control program starts fixed corresponding operation, thereby detecting the abnormal state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54030225A JPS6036147B2 (en) | 1979-03-15 | 1979-03-15 | Synchronous detection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54030225A JPS6036147B2 (en) | 1979-03-15 | 1979-03-15 | Synchronous detection method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55123256A true JPS55123256A (en) | 1980-09-22 |
JPS6036147B2 JPS6036147B2 (en) | 1985-08-19 |
Family
ID=12297768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54030225A Expired JPS6036147B2 (en) | 1979-03-15 | 1979-03-15 | Synchronous detection method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6036147B2 (en) |
-
1979
- 1979-03-15 JP JP54030225A patent/JPS6036147B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6036147B2 (en) | 1985-08-19 |
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