JPS55118174A - Electronic desk computer - Google Patents

Electronic desk computer

Info

Publication number
JPS55118174A
JPS55118174A JP2545079A JP2545079A JPS55118174A JP S55118174 A JPS55118174 A JP S55118174A JP 2545079 A JP2545079 A JP 2545079A JP 2545079 A JP2545079 A JP 2545079A JP S55118174 A JPS55118174 A JP S55118174A
Authority
JP
Japan
Prior art keywords
circuit
arithmetic result
display
disappearance
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2545079A
Other languages
Japanese (ja)
Inventor
Teruaki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2545079A priority Critical patent/JPS55118174A/en
Publication of JPS55118174A publication Critical patent/JPS55118174A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To give protection to disappearance of the arithmetic result for the electronic desk computer where the power switch is turned off automatically in case no operation is given for a fixed time or more, by giving the previous notice before turn-off of the power supply.
CONSTITUTION: With supply of the numerical value or the like to key input circuit 1, the operation is carried out through arithmetic control circuit 3. And the arithmetic result is memorized in display data memory circuit 2. At this moment, the signal is delivered to display signal generator circuit 4 from circuit 3 and then displayed to display circuit 8 through AND gate 7. In case the key operation is not given within circuit 3 for fixed time T1 or more, the NAND gate and delay circuit 9 deliver "1" and "0" with the fixed cycle. And circuit 8 displays the arithmetic result intermittently. After time T2 (T2>T1), circuit 3 opens switch 6 to cut off power supply 10. And the key operation is urged by the display flashing, thus avoiding the disappearance of the necessary arithmetic result.
COPYRIGHT: (C)1980,JPO&Japio
JP2545079A 1979-03-05 1979-03-05 Electronic desk computer Pending JPS55118174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2545079A JPS55118174A (en) 1979-03-05 1979-03-05 Electronic desk computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2545079A JPS55118174A (en) 1979-03-05 1979-03-05 Electronic desk computer

Publications (1)

Publication Number Publication Date
JPS55118174A true JPS55118174A (en) 1980-09-10

Family

ID=12166345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2545079A Pending JPS55118174A (en) 1979-03-05 1979-03-05 Electronic desk computer

Country Status (1)

Country Link
JP (1) JPS55118174A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339839A (en) * 1976-09-24 1978-04-12 Sharp Corp Key control type electronic device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339839A (en) * 1976-09-24 1978-04-12 Sharp Corp Key control type electronic device

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