JPS55113370A - Semicondcutor device - Google Patents

Semicondcutor device

Info

Publication number
JPS55113370A
JPS55113370A JP2046879A JP2046879A JPS55113370A JP S55113370 A JPS55113370 A JP S55113370A JP 2046879 A JP2046879 A JP 2046879A JP 2046879 A JP2046879 A JP 2046879A JP S55113370 A JPS55113370 A JP S55113370A
Authority
JP
Japan
Prior art keywords
region
layer
diffusion
type
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2046879A
Other languages
Japanese (ja)
Inventor
Yasunori Kanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2046879A priority Critical patent/JPS55113370A/en
Publication of JPS55113370A publication Critical patent/JPS55113370A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To make the electrical characteristic of the obtained device such that a high electric field is available in spite of a low voltage application by a method wherein a constant current elements to ve provided at a semicondcutor, device are formed along the logitudinal direction of the device.
CONSTITUTION: An n+-type buried region 2 is formed by diffusion on a p-type substrate and a n--type layer 3 is formed all over the surface with epitaxial growth and with the same process the region 2 is made to develop beneath the layer 3. Next thereto the layer 3 including the region 2 is isolated by a isolation region to shape the island region and at a edge of it an n+-type contact region 6 which is connected to the region 2 is formed by diffusion. On the other hand above the another edge of the layer 2 on the region 3 an n+-type contact region 5 is formed by diffusion in the same way, and at this edge thickness W of the layer 3 between region 5 and 3 is made to be narrower. After this process all surface is covered by a field insulating layer 4 and openings are provided on the region 5 and 6 and the electrodes 7 and 8 are connected and a electric source 9 is connected between them disposed electrode 7 as positive. Thus only low voltage is needed to raise the necessary field strength for obtaining constant current characteristic and an element utilizing scattering limited velocity is available.
COPYRIGHT: (C)1980,JPO&Japio
JP2046879A 1979-02-23 1979-02-23 Semicondcutor device Pending JPS55113370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2046879A JPS55113370A (en) 1979-02-23 1979-02-23 Semicondcutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2046879A JPS55113370A (en) 1979-02-23 1979-02-23 Semicondcutor device

Publications (1)

Publication Number Publication Date
JPS55113370A true JPS55113370A (en) 1980-09-01

Family

ID=12027920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2046879A Pending JPS55113370A (en) 1979-02-23 1979-02-23 Semicondcutor device

Country Status (1)

Country Link
JP (1) JPS55113370A (en)

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