JPS55110966A - Driver circuit - Google Patents

Driver circuit

Info

Publication number
JPS55110966A
JPS55110966A JP1882479A JP1882479A JPS55110966A JP S55110966 A JPS55110966 A JP S55110966A JP 1882479 A JP1882479 A JP 1882479A JP 1882479 A JP1882479 A JP 1882479A JP S55110966 A JPS55110966 A JP S55110966A
Authority
JP
Japan
Prior art keywords
circuit
driver circuit
load current
output
allowable level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1882479A
Other languages
Japanese (ja)
Inventor
Kenichi Nagatome
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1882479A priority Critical patent/JPS55110966A/en
Publication of JPS55110966A publication Critical patent/JPS55110966A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To prevent the driver circuit from overcurrent flowing by making the output of the driver circuit higher in the impedance when the load current flowing to the circuit of a test evaluation device in the semi-conductor integrated circuit exceeds the allowable level.
CONSTITUTION: The load current I0 flowing through the driver circuit 1 is obtained by detecting the differential voltage across the series resistor 2 connected between the driver circuit 1 and the tested semiconductor integrated circuit. The controlling circuit 7 determines whether the load current I0 exceeds the allowable level IL set by the circuit 6 or not. When I0>IL, the output signal of the circuit 7 and the input/output change-over signal is applied to an OR gate 8. This makes the output impedance of the driver circuit 1 higher not only at the output mode of the DUT terminal 4 but also when the load current I0 exceeding the allowable level IL flows whereby the load current is cut off to protect the driver circuit 1.
COPYRIGHT: (C)1980,JPO&Japio
JP1882479A 1979-02-20 1979-02-20 Driver circuit Pending JPS55110966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1882479A JPS55110966A (en) 1979-02-20 1979-02-20 Driver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1882479A JPS55110966A (en) 1979-02-20 1979-02-20 Driver circuit

Publications (1)

Publication Number Publication Date
JPS55110966A true JPS55110966A (en) 1980-08-27

Family

ID=11982300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1882479A Pending JPS55110966A (en) 1979-02-20 1979-02-20 Driver circuit

Country Status (1)

Country Link
JP (1) JPS55110966A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10603235B2 (en) 2013-03-15 2020-03-31 Hillenbrand Management Company Llc Patient repositioning system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10603235B2 (en) 2013-03-15 2020-03-31 Hillenbrand Management Company Llc Patient repositioning system
US11026853B2 (en) 2013-03-15 2021-06-08 Hillenbrand Management Company Llc Patient repositioning system

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