JPS55105881A - Buffer memory system - Google Patents

Buffer memory system

Info

Publication number
JPS55105881A
JPS55105881A JP1007279A JP1007279A JPS55105881A JP S55105881 A JPS55105881 A JP S55105881A JP 1007279 A JP1007279 A JP 1007279A JP 1007279 A JP1007279 A JP 1007279A JP S55105881 A JPS55105881 A JP S55105881A
Authority
JP
Japan
Prior art keywords
memory
buffer memory
cpu11
interface
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1007279A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1007279A priority Critical patent/JPS55105881A/en
Publication of JPS55105881A publication Critical patent/JPS55105881A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To omit the alteration or exchange for the hardware in case the buffer memory is added or deleted, by securing the same interface between the CPU and the buffer memory as well as between the buffer memory and the main memory each.
CONSTITUTION: Buffer memory 13 is provided independently between CPU11 and main memory 12. And the same constitution is secured for the interface between CPU11 and memory 13 as well as the interface between memory 13 and main memory 12. In such constitution, memory 13 is removed to secure the direct connection between CPU11 and memory 12, or the buffer memory is added. In such case, no alteration nor exchange is required for the interface hardware of CPU11 and memory 12.
COPYRIGHT: (C)1980,JPO&Japio
JP1007279A 1979-01-31 1979-01-31 Buffer memory system Pending JPS55105881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1007279A JPS55105881A (en) 1979-01-31 1979-01-31 Buffer memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1007279A JPS55105881A (en) 1979-01-31 1979-01-31 Buffer memory system

Publications (1)

Publication Number Publication Date
JPS55105881A true JPS55105881A (en) 1980-08-13

Family

ID=11740157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1007279A Pending JPS55105881A (en) 1979-01-31 1979-01-31 Buffer memory system

Country Status (1)

Country Link
JP (1) JPS55105881A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6085297A (en) * 1996-08-09 2000-07-04 Nec Corporation Single-chip memory system including buffer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4962038A (en) * 1972-10-12 1974-06-15
JPS5187927A (en) * 1975-01-31 1976-07-31 Hitachi Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4962038A (en) * 1972-10-12 1974-06-15
JPS5187927A (en) * 1975-01-31 1976-07-31 Hitachi Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6085297A (en) * 1996-08-09 2000-07-04 Nec Corporation Single-chip memory system including buffer

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