JPS55105438A - Logic array - Google Patents

Logic array

Info

Publication number
JPS55105438A
JPS55105438A JP1294979A JP1294979A JPS55105438A JP S55105438 A JPS55105438 A JP S55105438A JP 1294979 A JP1294979 A JP 1294979A JP 1294979 A JP1294979 A JP 1294979A JP S55105438 A JPS55105438 A JP S55105438A
Authority
JP
Japan
Prior art keywords
array
decoder
potential
diode
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1294979A
Other languages
Japanese (ja)
Inventor
Akira Aso
Hiromichi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1294979A priority Critical patent/JPS55105438A/en
Publication of JPS55105438A publication Critical patent/JPS55105438A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase the using allowance range for the AND array by using the transistor circuit containing the constant current source to be connected to the emitter coupling for the means which transmits the output signal of the decoder circuit to the AND array. CONSTITUTION:When output level Zn and Zn' of the decoder become to the high levels along with points a-f reaching the higher potential than reference voltage VRR, corresponding transistors Q1-Qn are turned on. And furthermore corresponding bit lines of 1-n turn to the low levels respectively. The low-level potential of the bit line then is identical to potential Vn-VDn+VF which is clamped by Di, where Vn is the constant voltage due to the constant current gate of the decoder, and VF is the forward bias voltage of the diode in the array each. The clamping effect of diode Di prevents the current flowing through transistor Qn from becoming excessive and thus keeps the bit line at the normal level. In addition, the array current is increased by the clamping effect, thus increasing the speed.
JP1294979A 1979-02-07 1979-02-07 Logic array Pending JPS55105438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1294979A JPS55105438A (en) 1979-02-07 1979-02-07 Logic array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1294979A JPS55105438A (en) 1979-02-07 1979-02-07 Logic array

Publications (1)

Publication Number Publication Date
JPS55105438A true JPS55105438A (en) 1980-08-13

Family

ID=11819523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1294979A Pending JPS55105438A (en) 1979-02-07 1979-02-07 Logic array

Country Status (1)

Country Link
JP (1) JPS55105438A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132244A (en) * 1982-10-25 1984-07-30 バロ−ス・コ−ポレ−ション Logic array
JPS6258723A (en) * 1985-05-07 1987-03-14 フエアチヤイルド セミコンダクタ コ−ポレ−シヨン Depseudo signal circuit for digital logical circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54111747A (en) * 1978-02-22 1979-09-01 Nec Corp Drive circuit for matrix

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54111747A (en) * 1978-02-22 1979-09-01 Nec Corp Drive circuit for matrix

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132244A (en) * 1982-10-25 1984-07-30 バロ−ス・コ−ポレ−ション Logic array
JPS6258723A (en) * 1985-05-07 1987-03-14 フエアチヤイルド セミコンダクタ コ−ポレ−シヨン Depseudo signal circuit for digital logical circuit

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