JPS55104142A - Receiver with clocking function - Google Patents

Receiver with clocking function

Info

Publication number
JPS55104142A
JPS55104142A JP1121379A JP1121379A JPS55104142A JP S55104142 A JPS55104142 A JP S55104142A JP 1121379 A JP1121379 A JP 1121379A JP 1121379 A JP1121379 A JP 1121379A JP S55104142 A JPS55104142 A JP S55104142A
Authority
JP
Japan
Prior art keywords
frequency
signal
controller
clocking
reference frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1121379A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Okazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1121379A priority Critical patent/JPS55104142A/en
Publication of JPS55104142A publication Critical patent/JPS55104142A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Abstract

PURPOSE:To achieve the clocking of time and electronic tuning of receiver at the same time, by obtaining a comparison frequency and reference frequency through the frequency demultiplication of signal. CONSTITUTION:The signal is 4.5MHz of the reference frequency generator 15 is given to the controller 13 as the clock signal. Further, the reference frequency generator 15 frequency-divides 4.5MHz to produce the comparison frequency to the phase locked loop such 1kHz, 5kHz and 10kHz and it is fed to the phase comparator 10. When the signal corresponding to the frequency of the reception station with the channel selection switch in the switch group 12 is given to the controller 13, the frequency dividing ratio of the programmable frequency divider 9 is set by it. Further, the controller 13 counts the reference frequency clock for clocking. Accordingly, the constitution as a whole can be simplified.
JP1121379A 1979-02-02 1979-02-02 Receiver with clocking function Pending JPS55104142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1121379A JPS55104142A (en) 1979-02-02 1979-02-02 Receiver with clocking function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1121379A JPS55104142A (en) 1979-02-02 1979-02-02 Receiver with clocking function

Publications (1)

Publication Number Publication Date
JPS55104142A true JPS55104142A (en) 1980-08-09

Family

ID=11771699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1121379A Pending JPS55104142A (en) 1979-02-02 1979-02-02 Receiver with clocking function

Country Status (1)

Country Link
JP (1) JPS55104142A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5044753A (en) * 1973-08-24 1975-04-22
JPS5318919B2 (en) * 1972-05-19 1978-06-17

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318919B2 (en) * 1972-05-19 1978-06-17
JPS5044753A (en) * 1973-08-24 1975-04-22

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