JPS5494268A - Analog digital converter - Google Patents

Analog digital converter

Info

Publication number
JPS5494268A
JPS5494268A JP171878A JP171878A JPS5494268A JP S5494268 A JPS5494268 A JP S5494268A JP 171878 A JP171878 A JP 171878A JP 171878 A JP171878 A JP 171878A JP S5494268 A JPS5494268 A JP S5494268A
Authority
JP
Japan
Prior art keywords
charge
storage section
ccd
terminals
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP171878A
Other languages
Japanese (ja)
Other versions
JPS6013578B2 (en
Inventor
Shiro Horiuchi
Hiroshi Kadota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP171878A priority Critical patent/JPS6013578B2/en
Publication of JPS5494268A publication Critical patent/JPS5494268A/en
Publication of JPS6013578B2 publication Critical patent/JPS6013578B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To enable perfect circuit integration for AD converter, by enabling the high speed AD conversion up to the frequency of a half the clock frequency theoretically, through the use of CCD.
CONSTITUTION: The charge corresponding to the analog signal inputted from the terminal 120 of CCD 101 is transferred from left to right in the charge storage sections 102 to 110 with the two phase drive pulse fed to the terminals 126 and 127. One end of the charge storage section is provided with the discharge storage section 202 measuring a given amount of the transferred charge, detecting section 203 detecting the measured charge, and control gate 201 controlling the charge amount measured. The size of the charge storage section 202 determines the charge amount measured and the area of the gate electrode 201 is set so that it is the same for each storage section. Next, charge is fed to the code conversion circuit 220 with the delay circuits 204 to 211 connected to the detector 203 and set for the delay time shorter by one bit, and it is picked up as digital code from the terminals 221 to 223.
COPYRIGHT: (C)1979,JPO&Japio
JP171878A 1978-01-10 1978-01-10 analog to digital converter Expired JPS6013578B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP171878A JPS6013578B2 (en) 1978-01-10 1978-01-10 analog to digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP171878A JPS6013578B2 (en) 1978-01-10 1978-01-10 analog to digital converter

Publications (2)

Publication Number Publication Date
JPS5494268A true JPS5494268A (en) 1979-07-25
JPS6013578B2 JPS6013578B2 (en) 1985-04-08

Family

ID=11509337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP171878A Expired JPS6013578B2 (en) 1978-01-10 1978-01-10 analog to digital converter

Country Status (1)

Country Link
JP (1) JPS6013578B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339407B1 (en) * 1994-06-02 2002-10-25 주식회사 하이닉스반도체 Ccd analog/digital converter
KR100430411B1 (en) * 1999-01-08 2004-05-10 인텔 코오퍼레이션 Programmable incremental a/d converter for digital camera and image processing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339407B1 (en) * 1994-06-02 2002-10-25 주식회사 하이닉스반도체 Ccd analog/digital converter
KR100430411B1 (en) * 1999-01-08 2004-05-10 인텔 코오퍼레이션 Programmable incremental a/d converter for digital camera and image processing

Also Published As

Publication number Publication date
JPS6013578B2 (en) 1985-04-08

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