JPS5494240A - Multiplex artificial memory control unit - Google Patents

Multiplex artificial memory control unit

Info

Publication number
JPS5494240A
JPS5494240A JP86878A JP86878A JPS5494240A JP S5494240 A JPS5494240 A JP S5494240A JP 86878 A JP86878 A JP 86878A JP 86878 A JP86878 A JP 86878A JP S5494240 A JPS5494240 A JP S5494240A
Authority
JP
Japan
Prior art keywords
logic value
entry
address
false
sto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP86878A
Other languages
Japanese (ja)
Other versions
JPS6027050B2 (en
Inventor
Akira Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53000868A priority Critical patent/JPS6027050B2/en
Publication of JPS5494240A publication Critical patent/JPS5494240A/en
Publication of JPS6027050B2 publication Critical patent/JPS6027050B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To increase the performance, by making ineffective the entry having false logic value at the effective bit with replacement, by changing the logic value as to the entry having true logic value into false logic value, and by reducing the overhead of artificial space purge.
CONSTITUTION: When false logic value is memorized in the effective bit of the address converter 7, it is made conversion disable. The content of the STO stack point register 15 continues advancing, resulting in including the address of final entry among the entire entry of the STO address stack 4. Immediately after that, when the content of the STO address register 3 is set to the first entry of the stack, the entire entry is checked for the converter 7, and after replacement, the entry having false logic value to the effective bit is made ineffective, and as to the entry having the true logic value, the logic value is changed into false logic value. Thus, the overhead of artificial space purge for the system performance can be reduced and the performance can be improved.
COPYRIGHT: (C)1979,JPO&Japio
JP53000868A 1978-01-10 1978-01-10 Multiple virtual memory controller Expired JPS6027050B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53000868A JPS6027050B2 (en) 1978-01-10 1978-01-10 Multiple virtual memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53000868A JPS6027050B2 (en) 1978-01-10 1978-01-10 Multiple virtual memory controller

Publications (2)

Publication Number Publication Date
JPS5494240A true JPS5494240A (en) 1979-07-25
JPS6027050B2 JPS6027050B2 (en) 1985-06-27

Family

ID=11485641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53000868A Expired JPS6027050B2 (en) 1978-01-10 1978-01-10 Multiple virtual memory controller

Country Status (1)

Country Link
JP (1) JPS6027050B2 (en)

Also Published As

Publication number Publication date
JPS6027050B2 (en) 1985-06-27

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