JPS5492115A - Picture compressing system - Google Patents

Picture compressing system

Info

Publication number
JPS5492115A
JPS5492115A JP15947377A JP15947377A JPS5492115A JP S5492115 A JPS5492115 A JP S5492115A JP 15947377 A JP15947377 A JP 15947377A JP 15947377 A JP15947377 A JP 15947377A JP S5492115 A JPS5492115 A JP S5492115A
Authority
JP
Japan
Prior art keywords
unit information
circuit
information
rate
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15947377A
Other languages
Japanese (ja)
Inventor
Michiaki Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15947377A priority Critical patent/JPS5492115A/en
Publication of JPS5492115A publication Critical patent/JPS5492115A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the memory capacity and transfering rate and to compress pectures that can be restored to the original picture at the rate of 1 : 1 by comparing with each preceeding information and memorizing only the unit information having different portions.
CONSTITUTION: The picture compression circuit "crams" the video from photoelectric conversion device 1 with a sample circuit and completely "restore" the video to the rate of 1 : 1. It consists of controller 2, AND circuits 3 and 7, buffer register BR4 and 6, EOR circuit group 8, address counter 9 and 12, and memory units 10 and 11. When for instance the unit information that has been input into BR6 is the first unit information of the second line, exclusive OR 8a is processed for the first unit information of BR5 information in circuit group 8 and, furthermore, the result is processed by "OR" circuit 8. In this case, if the result shows that both unit information consist of completely same bit structures, "0" is output and if they are different, "1" is output. The controller 2 counts up address counter 12.
COPYRIGHT: (C)1979,JPO&Japio
JP15947377A 1977-12-29 1977-12-29 Picture compressing system Pending JPS5492115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15947377A JPS5492115A (en) 1977-12-29 1977-12-29 Picture compressing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15947377A JPS5492115A (en) 1977-12-29 1977-12-29 Picture compressing system

Publications (1)

Publication Number Publication Date
JPS5492115A true JPS5492115A (en) 1979-07-21

Family

ID=15694530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15947377A Pending JPS5492115A (en) 1977-12-29 1977-12-29 Picture compressing system

Country Status (1)

Country Link
JP (1) JPS5492115A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046424A (en) * 1973-08-31 1975-04-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046424A (en) * 1973-08-31 1975-04-25

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