JPS5491119A - Feed folding circuit - Google Patents

Feed folding circuit

Info

Publication number
JPS5491119A
JPS5491119A JP15900877A JP15900877A JPS5491119A JP S5491119 A JPS5491119 A JP S5491119A JP 15900877 A JP15900877 A JP 15900877A JP 15900877 A JP15900877 A JP 15900877A JP S5491119 A JPS5491119 A JP S5491119A
Authority
JP
Japan
Prior art keywords
feeder
capacitor
output circuit
feed
induced voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15900877A
Other languages
Japanese (ja)
Other versions
JPS6143902B2 (en
Inventor
Akimasa Yamazaki
Takao Sato
Hitoshi Hiraike
Haruo Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15900877A priority Critical patent/JPS5491119A/en
Publication of JPS5491119A publication Critical patent/JPS5491119A/en
Publication of JPS6143902B2 publication Critical patent/JPS6143902B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/28—Reducing interference caused by currents induced in cable sheathing or armouring

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To suppress the induced voltage generated in feeders, by inserting a suppression circuit using transistors between a feed circuit and an output circuit in the communication system where a pair of balanced cables are used to perform signal transmission by remoet feed. CONSTITUTION:The emitter of transistor 12 is connected to the intermediate point of output circuit 5 of terminal equipment 1. Impedance of terminal equipment 1 at the view from feeder 10 can be made higher by resistance 14. As a result, the time constant between capacitor 13 and impedance of the feeder can be longer even if capacitor 13 has not a large capacity, and the AC induced voltage generated in the feeder at the connection point of resistance 14 and capacitor 13 is suppressed to obtain an approximately fixed voltage. Meanwhile, the fluctuation of the voltage in the feeder is absorbed by VCE of transistor 12, and influences of the induced voltage on output circuit 5 can be eliminated.
JP15900877A 1977-12-28 1977-12-28 Feed folding circuit Granted JPS5491119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15900877A JPS5491119A (en) 1977-12-28 1977-12-28 Feed folding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15900877A JPS5491119A (en) 1977-12-28 1977-12-28 Feed folding circuit

Publications (2)

Publication Number Publication Date
JPS5491119A true JPS5491119A (en) 1979-07-19
JPS6143902B2 JPS6143902B2 (en) 1986-09-30

Family

ID=15684217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15900877A Granted JPS5491119A (en) 1977-12-28 1977-12-28 Feed folding circuit

Country Status (1)

Country Link
JP (1) JPS5491119A (en)

Also Published As

Publication number Publication date
JPS6143902B2 (en) 1986-09-30

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