JPS5487464A - Code pulse generator circuit - Google Patents

Code pulse generator circuit

Info

Publication number
JPS5487464A
JPS5487464A JP15577677A JP15577677A JPS5487464A JP S5487464 A JPS5487464 A JP S5487464A JP 15577677 A JP15577677 A JP 15577677A JP 15577677 A JP15577677 A JP 15577677A JP S5487464 A JPS5487464 A JP S5487464A
Authority
JP
Japan
Prior art keywords
pulse
signal
output
gate
pulse generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15577677A
Other languages
Japanese (ja)
Inventor
Yoshio Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15577677A priority Critical patent/JPS5487464A/en
Publication of JPS5487464A publication Critical patent/JPS5487464A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make it possible to adjust an output pulse width and pulse interval by eliminating the trailing edge of a code pulse by finding AND between the final output and an output one stage before of a shift register. CONSTITUTION:By gate signal (a), oscillator 1 supplies clock (b) to shift register 2 and parallel input 3 is so set that final output Qn9 of register 2 will be pulse (c). As a result, pulse (d) appears at output Qn-110 one stage before and a pulse obtained by inverting 11 pulse (d) and signal (e) obtained by delaying 8 signal (a) are passed through NAND gate 12 to obtain pulse (f), which is differentiated 13 to obtain signal (g), so that signal (h) can be obtained by inverting 14 signal (g). In addition, signal (h) is differentiated 15 to obtain signal (i) and signals (c), (i) and (a) are supplied to AND gate 16, thereby obtaining its output pulse (j). Consequently, the width and interval of code pulses can be set freely.
JP15577677A 1977-12-23 1977-12-23 Code pulse generator circuit Pending JPS5487464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15577677A JPS5487464A (en) 1977-12-23 1977-12-23 Code pulse generator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15577677A JPS5487464A (en) 1977-12-23 1977-12-23 Code pulse generator circuit

Publications (1)

Publication Number Publication Date
JPS5487464A true JPS5487464A (en) 1979-07-11

Family

ID=15613149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15577677A Pending JPS5487464A (en) 1977-12-23 1977-12-23 Code pulse generator circuit

Country Status (1)

Country Link
JP (1) JPS5487464A (en)

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