JPS5487020A - Key input system - Google Patents

Key input system

Info

Publication number
JPS5487020A
JPS5487020A JP15474377A JP15474377A JPS5487020A JP S5487020 A JPS5487020 A JP S5487020A JP 15474377 A JP15474377 A JP 15474377A JP 15474377 A JP15474377 A JP 15474377A JP S5487020 A JPS5487020 A JP S5487020A
Authority
JP
Japan
Prior art keywords
key
keys
signal
cleared
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15474377A
Other languages
Japanese (ja)
Other versions
JPS605007B2 (en
Inventor
Hidetaka Fujisawa
Toshifumi Hoshii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP52154743A priority Critical patent/JPS605007B2/en
Publication of JPS5487020A publication Critical patent/JPS5487020A/en
Publication of JPS605007B2 publication Critical patent/JPS605007B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To realize a key input system in which the operation signal of the specified kay among plural number of keys can be accepted before the other keys are switched on and the input signal is cleared and which can carry out the necessary processes following the acceptance of the operation signal.
CONSTITUTION: With push of start key ST of the stopwatch, counter 10 is reset by control signal C2 to start the counting. The count value is sent to arithmetic circuit 3 by control signal C2 to be written into register M1 of RAM4. Then the contents are added together between M1 and M2 to be written into M2 and then to reset counter 10. With repetition of the above processes, the timing information is memorized in M2. Here, the ST key is specified, and thus the input signal of key St can be accepted even before the input signals of other keys are cleared.
COPYRIGHT: (C)1979,JPO&Japio
JP52154743A 1977-12-22 1977-12-22 Key input method Expired JPS605007B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52154743A JPS605007B2 (en) 1977-12-22 1977-12-22 Key input method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52154743A JPS605007B2 (en) 1977-12-22 1977-12-22 Key input method

Publications (2)

Publication Number Publication Date
JPS5487020A true JPS5487020A (en) 1979-07-11
JPS605007B2 JPS605007B2 (en) 1985-02-07

Family

ID=15590937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52154743A Expired JPS605007B2 (en) 1977-12-22 1977-12-22 Key input method

Country Status (1)

Country Link
JP (1) JPS605007B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61197603U (en) * 1985-05-31 1986-12-10

Also Published As

Publication number Publication date
JPS605007B2 (en) 1985-02-07

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