JPS5484950A - Variable attenuation equalizer - Google Patents
Variable attenuation equalizerInfo
- Publication number
- JPS5484950A JPS5484950A JP15245777A JP15245777A JPS5484950A JP S5484950 A JPS5484950 A JP S5484950A JP 15245777 A JP15245777 A JP 15245777A JP 15245777 A JP15245777 A JP 15245777A JP S5484950 A JPS5484950 A JP S5484950A
- Authority
- JP
- Japan
- Prior art keywords
- adder
- multiplier
- variable
- output
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
- H04B3/143—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers
- H04B3/145—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers variable equalisers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To proportionally shift the frequency versus attenuation performance of the input signal sampled at the frequency band toward attenuation, by constituting the variable attenuation equalizer with the combination of simple elements. CONSTITUTION:The first adder 4 inputting input signal via the fixed multiplier and the second adder 5 inputting the output of the adder 4 via the second fixed multiplier 7 are provided. Further, the adder 5 is provided with the fixed multiplier 3, which receives the output of the post stage of the filter block 1 including the variable multiplier 2 and delay circit receiving the output of the adder 4. Further, the variable attenuation equalizer is constituted by providing the fixed adder 8 which receives the output at the post stage of the filter block 1 and adds it to the adder 4 in feedback manner. In addition, the variable multiplier 2' of the filter block 1 including the variable attenuator 2 and delay circuit is connected to the pre-stage and the output of the variable multiplier 2' at the pre-stage is added to the adder 5 via the fixed multiplier 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15245777A JPS5484950A (en) | 1977-12-20 | 1977-12-20 | Variable attenuation equalizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15245777A JPS5484950A (en) | 1977-12-20 | 1977-12-20 | Variable attenuation equalizer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5484950A true JPS5484950A (en) | 1979-07-06 |
JPS6113654B2 JPS6113654B2 (en) | 1986-04-15 |
Family
ID=15540926
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15245777A Granted JPS5484950A (en) | 1977-12-20 | 1977-12-20 | Variable attenuation equalizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5484950A (en) |
-
1977
- 1977-12-20 JP JP15245777A patent/JPS5484950A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6113654B2 (en) | 1986-04-15 |
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