JPS5484942A - Multiplying circuit - Google Patents

Multiplying circuit

Info

Publication number
JPS5484942A
JPS5484942A JP15235777A JP15235777A JPS5484942A JP S5484942 A JPS5484942 A JP S5484942A JP 15235777 A JP15235777 A JP 15235777A JP 15235777 A JP15235777 A JP 15235777A JP S5484942 A JPS5484942 A JP S5484942A
Authority
JP
Japan
Prior art keywords
multiplication
bit
module
rank
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15235777A
Other languages
Japanese (ja)
Inventor
Shigeki Shibayama
Kazuhide Iwata
Nobuo Okuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15235777A priority Critical patent/JPS5484942A/en
Publication of JPS5484942A publication Critical patent/JPS5484942A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To enable the multiplication of 2n-bit with the multiplier of n-bit, by using the multiplier LSI constitution and by combinating the adder of two stage constitution obtaining a part of the result of multiplication for the multiplier. CONSTITUTION:In the circuit performing multiplication for the first and second codes LSP1, LSP2 and MSP1 and MSP2 of 2n-bit, the multiplication module 4 performing the multiplication of lower n-bit of the first and second data and the multiplication module 1 performing the multiplication for the upper rank n-bit are provided. Further, the multiplication module 3 performing the multiplication for the lower rank n-bit of the first data and the upper rank n-bit for the second data, and the multiplication module 2 for the upper rank n-bit of the first data and the lower rank n-bit of the second data are provided. Moreover, the code control circuit 11 adding the result of multiplication of the lower rank n-bit of the modules 2 and 3 to the upper rank n-bit of the result of multiplication of the module 4, adders 5 to 7, and adders 8 to 10 adding the upper rank n-bit of the result of multiplication of the modules 2 and 3 to the lower rank n-bit of the result of multiplication of the module 2 are provided.
JP15235777A 1977-12-20 1977-12-20 Multiplying circuit Pending JPS5484942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15235777A JPS5484942A (en) 1977-12-20 1977-12-20 Multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15235777A JPS5484942A (en) 1977-12-20 1977-12-20 Multiplying circuit

Publications (1)

Publication Number Publication Date
JPS5484942A true JPS5484942A (en) 1979-07-06

Family

ID=15538766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15235777A Pending JPS5484942A (en) 1977-12-20 1977-12-20 Multiplying circuit

Country Status (1)

Country Link
JP (1) JPS5484942A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58144259A (en) * 1982-02-19 1983-08-27 Sony Corp Digital signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58144259A (en) * 1982-02-19 1983-08-27 Sony Corp Digital signal processor

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