JPS5479377A - Method of controlling sequence - Google Patents

Method of controlling sequence

Info

Publication number
JPS5479377A
JPS5479377A JP14645677A JP14645677A JPS5479377A JP S5479377 A JPS5479377 A JP S5479377A JP 14645677 A JP14645677 A JP 14645677A JP 14645677 A JP14645677 A JP 14645677A JP S5479377 A JPS5479377 A JP S5479377A
Authority
JP
Japan
Prior art keywords
sequence
conditional
code
conditions
relay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14645677A
Other languages
Japanese (ja)
Inventor
Tadahiro Yanagisawa
Matsuo Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14645677A priority Critical patent/JPS5479377A/en
Publication of JPS5479377A publication Critical patent/JPS5479377A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To make design easy, to simplify the conversion of control contents and to shorten time necessary for operation, in a method of controlling sequence by a stored program system.
CONSTITUTION: This sequence control method is shaped in such a manner that a code for designating the condition of conditions beforehand decided and an AND code for judging as to whether or not the conditions of operation are brought about from a code for assigning a location of a flag bit indicating the formation or failure of the conditions are written to a memory storage. In a sequence block diagram arranged in response to a relay sequence diagram containing conditional rules 1W4, logical circuits 21W24 are mounted in response to said conditional rules 1W4, and conditional signals AWC, E, F, D and conditional masks M2, M3, M4 are input to the AND circuits A and the mask register portions M of each logical circuit. An output circuit 2A provides a relay X with the output of the logical circuit 24.
COPYRIGHT: (C)1979,JPO&Japio
JP14645677A 1977-12-06 1977-12-06 Method of controlling sequence Pending JPS5479377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14645677A JPS5479377A (en) 1977-12-06 1977-12-06 Method of controlling sequence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14645677A JPS5479377A (en) 1977-12-06 1977-12-06 Method of controlling sequence

Publications (1)

Publication Number Publication Date
JPS5479377A true JPS5479377A (en) 1979-06-25

Family

ID=15408041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14645677A Pending JPS5479377A (en) 1977-12-06 1977-12-06 Method of controlling sequence

Country Status (1)

Country Link
JP (1) JPS5479377A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330903A (en) * 1985-07-22 1988-02-09 ウエスチングハウス・エレクトリック・コーポレーション Preparation and execution of table driving logic for logical system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330903A (en) * 1985-07-22 1988-02-09 ウエスチングハウス・エレクトリック・コーポレーション Preparation and execution of table driving logic for logical system

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