JPS5475959A - Programmable logic array circuit - Google Patents

Programmable logic array circuit

Info

Publication number
JPS5475959A
JPS5475959A JP14274777A JP14274777A JPS5475959A JP S5475959 A JPS5475959 A JP S5475959A JP 14274777 A JP14274777 A JP 14274777A JP 14274777 A JP14274777 A JP 14274777A JP S5475959 A JPS5475959 A JP S5475959A
Authority
JP
Japan
Prior art keywords
line
row
program
programmable logic
logic array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14274777A
Other languages
Japanese (ja)
Inventor
Suminori Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14274777A priority Critical patent/JPS5475959A/en
Publication of JPS5475959A publication Critical patent/JPS5475959A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the number of wirings required for a program by providing a switching element, which becomes conductive only at a program time, between conductors, which connect active elements arranged in the same line or row, by a single program line. CONSTITUTION:In programmable logic array PLA, the current flows from line driving transistor Trl3 to row driving Trll. At a program time, when switch 19 is connected to the side of bias voltage +VB, Tr16 is all turned on the make rows C1 and C1' into one conductor. Therefore, for example, the fuse at the crossover of row C1 and line R1 as well as the fuse at the corssover of row C', which is the output line of inverter 4, and line RN are made programmable. When switch 19 is grounded, I/O lines C1 to CN+1 and C1' to CN+1' of inverter 4, etc., are prevented from short-circuiting to execute a logic function because Tr16 is all turned off. As a result, the number of wirings required for a program can be reduced to reduce the area of PLA.
JP14274777A 1977-11-30 1977-11-30 Programmable logic array circuit Pending JPS5475959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14274777A JPS5475959A (en) 1977-11-30 1977-11-30 Programmable logic array circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14274777A JPS5475959A (en) 1977-11-30 1977-11-30 Programmable logic array circuit

Publications (1)

Publication Number Publication Date
JPS5475959A true JPS5475959A (en) 1979-06-18

Family

ID=15322628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14274777A Pending JPS5475959A (en) 1977-11-30 1977-11-30 Programmable logic array circuit

Country Status (1)

Country Link
JP (1) JPS5475959A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01245720A (en) * 1988-03-28 1989-09-29 Pioneer Electron Corp Synthesizer tuner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01245720A (en) * 1988-03-28 1989-09-29 Pioneer Electron Corp Synthesizer tuner

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