JPS5474341A - Inspection system for array element - Google Patents

Inspection system for array element

Info

Publication number
JPS5474341A
JPS5474341A JP14203877A JP14203877A JPS5474341A JP S5474341 A JPS5474341 A JP S5474341A JP 14203877 A JP14203877 A JP 14203877A JP 14203877 A JP14203877 A JP 14203877A JP S5474341 A JPS5474341 A JP S5474341A
Authority
JP
Japan
Prior art keywords
fpla
unit
product
work data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14203877A
Other languages
Japanese (ja)
Inventor
Takeo Matsunuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14203877A priority Critical patent/JPS5474341A/en
Publication of JPS5474341A publication Critical patent/JPS5474341A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To inspect whether an element has an expected logic function, judging from work data on a FPLA (field programmable logic array) element.
CONSTITUTION: Memory unit 7 is stored with FPLA-element work data. An inspection input is applied to both inspected FPLA element installation unit and product arithmetic unit 11. Through the operation of counter 8, work data are selected on a product-item line unit and selected memory contents are transmitted to integrating unit 11 and output selector 12. Judging from information at the intersection between product-item lines of a sum matrix, output selector 12 decides whether the arithmetic results of integrating unit 11 should be transmitted to latch circuit 13 or not. After this operation by all product-item lines, the output of the FPLA element is compared with the value of the latch circuit for its decision. On this system, the need of correct output results used as expected values is eliminated.
COPYRIGHT: (C)1979,JPO&Japio
JP14203877A 1977-11-25 1977-11-25 Inspection system for array element Pending JPS5474341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14203877A JPS5474341A (en) 1977-11-25 1977-11-25 Inspection system for array element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14203877A JPS5474341A (en) 1977-11-25 1977-11-25 Inspection system for array element

Publications (1)

Publication Number Publication Date
JPS5474341A true JPS5474341A (en) 1979-06-14

Family

ID=15305924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14203877A Pending JPS5474341A (en) 1977-11-25 1977-11-25 Inspection system for array element

Country Status (1)

Country Link
JP (1) JPS5474341A (en)

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