JPS5466052A - Digital process controller - Google Patents

Digital process controller

Info

Publication number
JPS5466052A
JPS5466052A JP13248777A JP13248777A JPS5466052A JP S5466052 A JPS5466052 A JP S5466052A JP 13248777 A JP13248777 A JP 13248777A JP 13248777 A JP13248777 A JP 13248777A JP S5466052 A JPS5466052 A JP S5466052A
Authority
JP
Japan
Prior art keywords
controller
correcting arithmetic
input signal
arithmetic
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13248777A
Other languages
Japanese (ja)
Inventor
Hisanori Miyagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13248777A priority Critical patent/JPS5466052A/en
Publication of JPS5466052A publication Critical patent/JPS5466052A/en
Pending legal-status Critical Current

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  • Control By Computers (AREA)

Abstract

PURPOSE: To simplify manual operation in case of a trouble, and to reduce the cost of a device by commonly attaining the correcting arithmetic of a process input signal requiring correcting arithmetic, by providing a sensor module.
CONSTITUTION: This controller is provided with digital sub-loop controllers 21 to 2n controlling sub-loops of a process, host computer 1 giving various command signals to controllers 2, sensor module 3 which performs required correcting arithmetic by fetching process input signal 17 requiring correcting arithmetic and supplies its output to computer 1, controller 2, indicator 4, and interlock circuit 6, common digital bus 15 through which signals are transferred between module 3 and controller 2 via computer 1, and bus controller 14 which controls generally bus 15. As a result, the correcting arithmetic of a process input signal requiring the correcting arithmetic can be attained by a common module.
COPYRIGHT: (C)1979,JPO&Japio
JP13248777A 1977-11-07 1977-11-07 Digital process controller Pending JPS5466052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13248777A JPS5466052A (en) 1977-11-07 1977-11-07 Digital process controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13248777A JPS5466052A (en) 1977-11-07 1977-11-07 Digital process controller

Publications (1)

Publication Number Publication Date
JPS5466052A true JPS5466052A (en) 1979-05-28

Family

ID=15082514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13248777A Pending JPS5466052A (en) 1977-11-07 1977-11-07 Digital process controller

Country Status (1)

Country Link
JP (1) JPS5466052A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226305A (en) * 1989-02-28 1990-09-07 Nec Corp Equipment device controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226305A (en) * 1989-02-28 1990-09-07 Nec Corp Equipment device controller

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