JPS5462876A - Speed detector - Google Patents

Abstract

PURPOSE: To make possible detection of speed information in a counter by counting down or up the counter with the signals divided down from clock pulses through a programmable divider whose frequency dividing ratio changes at specified time intervals.

CONSTITUTION: A pulse generating circuit 36 generates clock pulses 40 to become a reference, which are then sent to a programmable divider 37. The set frequency of the pulses 40 is V₀/T₀ and V₀ number of pulses are produced during the period T₀. The divider 37 is so programmed that the frequency dividing ratio 1/N of the input signals is changed according to the time (t). With the time t = 0 when a reset signal 42 is produced at the rise of a position signal 9 as a start point, the frequency dividing ratio changes according to the program, thus the contents of a speed counter 38 are counted down to 2V₀ at t = 0, V₀ at t = T₀ and V₀/2 at t = 2T₀. When the signal 42 is produced at the time t = T (period of the position signal 9), the content of the counter 38 immediately before that is outputted as a current speed signal 20, thus the speeds may be directly detected at a high speed and low cost.

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