JPS5458317A - Detection system of address conincidence - Google Patents

Detection system of address conincidence

Info

Publication number
JPS5458317A
JPS5458317A JP12539677A JP12539677A JPS5458317A JP S5458317 A JPS5458317 A JP S5458317A JP 12539677 A JP12539677 A JP 12539677A JP 12539677 A JP12539677 A JP 12539677A JP S5458317 A JPS5458317 A JP S5458317A
Authority
JP
Japan
Prior art keywords
address
register
debug
coincidence
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12539677A
Other languages
Japanese (ja)
Inventor
Nobuyuki Watanabe
Hiroshi Kosugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12539677A priority Critical patent/JPS5458317A/en
Publication of JPS5458317A publication Critical patent/JPS5458317A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To make efficient the program debugging, by detecting the address coincidence through the performance of debug interrupt or debug stop only in the logic address designated in the designated logic space. CONSTITUTION:The comparator 6 outputs ''1'' when the content of the effective address register 1 is in agreement with that of the address register 5, and the comparator 9 outputs ''1'' when the content of the coincidence address register 7 is in agreement with that of the register 8. Then, if the specific bit s of the control register 12 is ''0'', the AND circuit 11 outputs the address coincidence detection signal if the outuputs of the comparators 6 and 9 are both ''1''. That is, only in the designated logic address in the designated logic space, dubug interrupt or debug stop is made, the address coincidence being detected. Thus, the program debug is efficiently made.
JP12539677A 1977-10-19 1977-10-19 Detection system of address conincidence Pending JPS5458317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12539677A JPS5458317A (en) 1977-10-19 1977-10-19 Detection system of address conincidence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12539677A JPS5458317A (en) 1977-10-19 1977-10-19 Detection system of address conincidence

Publications (1)

Publication Number Publication Date
JPS5458317A true JPS5458317A (en) 1979-05-11

Family

ID=14909094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12539677A Pending JPS5458317A (en) 1977-10-19 1977-10-19 Detection system of address conincidence

Country Status (1)

Country Link
JP (1) JPS5458317A (en)

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