JPS5448176A - Test method for semiconductor integrated circuit - Google Patents

Test method for semiconductor integrated circuit

Info

Publication number
JPS5448176A
JPS5448176A JP11486177A JP11486177A JPS5448176A JP S5448176 A JPS5448176 A JP S5448176A JP 11486177 A JP11486177 A JP 11486177A JP 11486177 A JP11486177 A JP 11486177A JP S5448176 A JPS5448176 A JP S5448176A
Authority
JP
Japan
Prior art keywords
circuit
supplied
comparator
relay
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11486177A
Other languages
Japanese (ja)
Inventor
Takashi Yamaguchi
Koichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11486177A priority Critical patent/JPS5448176A/en
Publication of JPS5448176A publication Critical patent/JPS5448176A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a test method for IC which can carry out the IC test independently from the function test and can reduce the test time.
CONSTITUTION: When the fault is detected for electrode terminal 16 amoun terminals 1W16 contained in IC container 20, relay K1 is actuated and terminal 16 is connected to comparator CM1 of comparator circuit 50 via contact 1a and 1b of relay K1 plus detection lead MS1. Other relays K2WK16 have no actuation, and terminals 1W15 are connected to the ground of power source 30 via relay contacts 2aW16a. and comparators CM2WCM16 are connected to VCC of power source 30 via contacts 2bW16b. As a result, detection output VX is produced at terminal 16 and then compared with comparison reference voltage Vr through CM1. The output of the comparator is supplied to OR circuit 60. In case voltage VX is lower than Vr, the defective signal is supplied to circuit 60. Accordingly, the defective signal is produced to the output and supplied to display circuit 70 to display the result
COPYRIGHT: (C)1979,JPO&Japio
JP11486177A 1977-09-22 1977-09-22 Test method for semiconductor integrated circuit Pending JPS5448176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11486177A JPS5448176A (en) 1977-09-22 1977-09-22 Test method for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11486177A JPS5448176A (en) 1977-09-22 1977-09-22 Test method for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5448176A true JPS5448176A (en) 1979-04-16

Family

ID=14648524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11486177A Pending JPS5448176A (en) 1977-09-22 1977-09-22 Test method for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5448176A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371669A (en) * 1986-09-16 1988-04-01 Matsushita Electronics Corp Inspecting method for electronic circuit device
US6075377A (en) * 1996-05-28 2000-06-13 Nec Corporation Method of confirming connecting states of signal terminals in a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371669A (en) * 1986-09-16 1988-04-01 Matsushita Electronics Corp Inspecting method for electronic circuit device
US6075377A (en) * 1996-05-28 2000-06-13 Nec Corporation Method of confirming connecting states of signal terminals in a semiconductor device

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