JPS5434910B2 - - Google Patents
Info
- Publication number
- JPS5434910B2 JPS5434910B2 JP4140673A JP4140673A JPS5434910B2 JP S5434910 B2 JPS5434910 B2 JP S5434910B2 JP 4140673 A JP4140673 A JP 4140673A JP 4140673 A JP4140673 A JP 4140673A JP S5434910 B2 JPS5434910 B2 JP S5434910B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140673A JPS5434910B2 (enExample) | 1973-04-13 | 1973-04-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140673A JPS5434910B2 (enExample) | 1973-04-13 | 1973-04-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS49128260A JPS49128260A (enExample) | 1974-12-09 |
| JPS5434910B2 true JPS5434910B2 (enExample) | 1979-10-30 |
Family
ID=12607467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4140673A Expired JPS5434910B2 (enExample) | 1973-04-13 | 1973-04-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5434910B2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220132614A (ko) * | 2020-01-28 | 2022-09-30 | 도쿄엘렉트론가부시키가이샤 | 접합 장치 및 접합 방법 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5225265A (en) * | 1975-08-22 | 1977-02-25 | Fujitsu Ltd | Method of measuring accuracy of pattern on multilayered printed wiring board |
| JPS54155467A (en) * | 1978-05-29 | 1979-12-07 | Fujitsu Ltd | Method of producing multiilayer printed board |
| JPS56126999A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Reference pattern position automatic detecting system in internal layer of multilayer printed board or like |
| JP5359757B2 (ja) * | 2009-10-08 | 2013-12-04 | パナソニック株式会社 | 多層プリント配線板の位置認識マーク |
| KR20140099761A (ko) * | 2013-02-04 | 2014-08-13 | 삼성전기주식회사 | 다층인쇄회로기판 및 층간 정합도 측정 방법 |
-
1973
- 1973-04-13 JP JP4140673A patent/JPS5434910B2/ja not_active Expired
Non-Patent Citations (2)
| Title |
|---|
| PRINTED CIRCUITS HANDBOOK=1967 * |
| PRODUCTION ENGINEERING MEASURE FOR MULTILAYER PRINTED WIRING BOARD=1966 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220132614A (ko) * | 2020-01-28 | 2022-09-30 | 도쿄엘렉트론가부시키가이샤 | 접합 장치 및 접합 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS49128260A (enExample) | 1974-12-09 |