JPS5428056B1 - - Google Patents
Info
- Publication number
- JPS5428056B1 JPS5428056B1 JP6414072A JP6414072A JPS5428056B1 JP S5428056 B1 JPS5428056 B1 JP S5428056B1 JP 6414072 A JP6414072 A JP 6414072A JP 6414072 A JP6414072 A JP 6414072A JP S5428056 B1 JPS5428056 B1 JP S5428056B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Error Detection And Correction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19712134529 DE2134529A1 (de) | 1971-07-10 | 1971-07-10 | Verfahren zur fehlererkennung und -korrektur in aus dem speicher einer programmgesteuerten datenverarbeitungsanlage ausgelesenen informationswoertern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5428056B1 true JPS5428056B1 (enExample) | 1979-09-13 |
Family
ID=5813290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6414072A Pending JPS5428056B1 (enExample) | 1971-07-10 | 1972-06-28 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5428056B1 (enExample) |
| DE (1) | DE2134529A1 (enExample) |
| FR (1) | FR2146081A5 (enExample) |
| GB (1) | GB1402613A (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2246023B1 (enExample) * | 1973-09-05 | 1976-10-01 | Honeywell Bull Soc Ind | |
| US3999051A (en) * | 1974-07-05 | 1976-12-21 | Sperry Rand Corporation | Error logging in semiconductor storage units |
| US3893071A (en) * | 1974-08-19 | 1975-07-01 | Ibm | Multi level error correction system for high density memory |
| US4100403A (en) * | 1977-04-25 | 1978-07-11 | International Business Machines Corporation | Method and means for discriminating between systematic and noise-induced error in data extracted from word organized memory arrays |
| JPS598852B2 (ja) * | 1979-07-30 | 1984-02-28 | 富士通株式会社 | エラ−処理方式 |
| US4319357A (en) * | 1979-12-14 | 1982-03-09 | International Business Machines Corp. | Double error correction using single error correcting code |
| US4345328A (en) * | 1980-06-30 | 1982-08-17 | Sperry Corporation | ECC Check bit generation using through checking parity bits |
| US8612828B2 (en) * | 2009-12-22 | 2013-12-17 | Intel Corporation | Error correction mechanisms for 8-bit memory devices |
-
1971
- 1971-07-10 DE DE19712134529 patent/DE2134529A1/de active Pending
-
1972
- 1972-06-28 JP JP6414072A patent/JPS5428056B1/ja active Pending
- 1972-07-10 GB GB3215872A patent/GB1402613A/en not_active Expired
- 1972-07-10 FR FR7225776A patent/FR2146081A5/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2146081A5 (enExample) | 1973-02-23 |
| DE2134529A1 (de) | 1973-01-25 |
| GB1402613A (en) | 1975-08-13 |