JPS5427703A - Reduction method for floating capacity of scanning matrix wiring - Google Patents

Reduction method for floating capacity of scanning matrix wiring

Info

Publication number
JPS5427703A
JPS5427703A JP9356077A JP9356077A JPS5427703A JP S5427703 A JPS5427703 A JP S5427703A JP 9356077 A JP9356077 A JP 9356077A JP 9356077 A JP9356077 A JP 9356077A JP S5427703 A JPS5427703 A JP S5427703A
Authority
JP
Japan
Prior art keywords
floating capacity
reduction method
matrix wiring
scanning matrix
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9356077A
Other languages
Japanese (ja)
Other versions
JPS5653913B2 (en
Inventor
Shinichi Maeno
Takao Ueno
Takehiko Tsutsumi
Masami Miura
Koji Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP9356077A priority Critical patent/JPS5427703A/en
Publication of JPS5427703A publication Critical patent/JPS5427703A/en
Publication of JPS5653913B2 publication Critical patent/JPS5653913B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To realize a wiring floating capacity reducing method which is able to operate at a high speed with the short rise time of a read signal, by reducing the influence of the wiring floating capacity of a read line upon the circuit operation.
JP9356077A 1977-08-03 1977-08-03 Reduction method for floating capacity of scanning matrix wiring Granted JPS5427703A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9356077A JPS5427703A (en) 1977-08-03 1977-08-03 Reduction method for floating capacity of scanning matrix wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9356077A JPS5427703A (en) 1977-08-03 1977-08-03 Reduction method for floating capacity of scanning matrix wiring

Publications (2)

Publication Number Publication Date
JPS5427703A true JPS5427703A (en) 1979-03-02
JPS5653913B2 JPS5653913B2 (en) 1981-12-22

Family

ID=14085622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9356077A Granted JPS5427703A (en) 1977-08-03 1977-08-03 Reduction method for floating capacity of scanning matrix wiring

Country Status (1)

Country Link
JP (1) JPS5427703A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4891966A (en) * 1972-03-07 1973-11-29
JPS5246706A (en) * 1975-10-11 1977-04-13 Nippon Telegr & Teleph Corp <Ntt> Signal scanning system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4891966A (en) * 1972-03-07 1973-11-29
JPS5246706A (en) * 1975-10-11 1977-04-13 Nippon Telegr & Teleph Corp <Ntt> Signal scanning system

Also Published As

Publication number Publication date
JPS5653913B2 (en) 1981-12-22

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