JPS5425177A - Manufacture for mos type semiconductor integrated circuit device - Google Patents

Manufacture for mos type semiconductor integrated circuit device

Info

Publication number
JPS5425177A
JPS5425177A JP8981777A JP8981777A JPS5425177A JP S5425177 A JPS5425177 A JP S5425177A JP 8981777 A JP8981777 A JP 8981777A JP 8981777 A JP8981777 A JP 8981777A JP S5425177 A JPS5425177 A JP S5425177A
Authority
JP
Japan
Prior art keywords
manufacture
integrated circuit
type semiconductor
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8981777A
Other languages
Japanese (ja)
Other versions
JPS5937862B2 (en
Inventor
Hiroshi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP52089817A priority Critical patent/JPS5937862B2/en
Publication of JPS5425177A publication Critical patent/JPS5425177A/en
Publication of JPS5937862B2 publication Critical patent/JPS5937862B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To simplify the work, by omitting the design of complicated channel stopper pattern, only with the pattern synthesis for the source and drain pattern and the gate pattern.
COPYRIGHT: (C)1979,JPO&Japio
JP52089817A 1977-07-28 1977-07-28 Method for manufacturing MOS type semiconductor integrated circuit device Expired JPS5937862B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52089817A JPS5937862B2 (en) 1977-07-28 1977-07-28 Method for manufacturing MOS type semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52089817A JPS5937862B2 (en) 1977-07-28 1977-07-28 Method for manufacturing MOS type semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5425177A true JPS5425177A (en) 1979-02-24
JPS5937862B2 JPS5937862B2 (en) 1984-09-12

Family

ID=13981287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52089817A Expired JPS5937862B2 (en) 1977-07-28 1977-07-28 Method for manufacturing MOS type semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5937862B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047456A (en) * 1983-08-26 1985-03-14 Mitsubishi Electric Corp Semiconductor device
US4952522A (en) * 1987-06-30 1990-08-28 Mitsubishi Denki Kabushiki Kaisha Method of fabricating complementary semiconductor integrated circuits devices having an increased immunity to latch-up

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047456A (en) * 1983-08-26 1985-03-14 Mitsubishi Electric Corp Semiconductor device
US4952522A (en) * 1987-06-30 1990-08-28 Mitsubishi Denki Kabushiki Kaisha Method of fabricating complementary semiconductor integrated circuits devices having an increased immunity to latch-up

Also Published As

Publication number Publication date
JPS5937862B2 (en) 1984-09-12

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