JPS5419619A - Refresh control system - Google Patents

Refresh control system

Info

Publication number
JPS5419619A
JPS5419619A JP8414177A JP8414177A JPS5419619A JP S5419619 A JPS5419619 A JP S5419619A JP 8414177 A JP8414177 A JP 8414177A JP 8414177 A JP8414177 A JP 8414177A JP S5419619 A JPS5419619 A JP S5419619A
Authority
JP
Japan
Prior art keywords
control system
refresh control
memory unit
lowering
execute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8414177A
Other languages
Japanese (ja)
Inventor
Noriyuki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8414177A priority Critical patent/JPS5419619A/en
Publication of JPS5419619A publication Critical patent/JPS5419619A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To execute the refresh operation without lowering the processing efficiency of the memory unit, in the memory unit using a dynamic type RAM.
JP8414177A 1977-07-15 1977-07-15 Refresh control system Pending JPS5419619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8414177A JPS5419619A (en) 1977-07-15 1977-07-15 Refresh control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8414177A JPS5419619A (en) 1977-07-15 1977-07-15 Refresh control system

Publications (1)

Publication Number Publication Date
JPS5419619A true JPS5419619A (en) 1979-02-14

Family

ID=13822209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8414177A Pending JPS5419619A (en) 1977-07-15 1977-07-15 Refresh control system

Country Status (1)

Country Link
JP (1) JPS5419619A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54106138A (en) * 1978-02-08 1979-08-20 Hitachi Ltd Memory refresh control system
JPS60696A (en) * 1983-06-16 1985-01-05 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory
JPH01227299A (en) * 1988-03-08 1989-09-11 Fujitsu Ltd Refresh control system for memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831030A (en) * 1971-08-26 1973-04-24
JPS5042754A (en) * 1973-08-20 1975-04-18
JPS5265630A (en) * 1975-11-27 1977-05-31 Nec Corp Refresh controll circuit
JPS5277640A (en) * 1975-12-24 1977-06-30 Nippon Telegr & Teleph Corp <Ntt> Refresh control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831030A (en) * 1971-08-26 1973-04-24
JPS5042754A (en) * 1973-08-20 1975-04-18
JPS5265630A (en) * 1975-11-27 1977-05-31 Nec Corp Refresh controll circuit
JPS5277640A (en) * 1975-12-24 1977-06-30 Nippon Telegr & Teleph Corp <Ntt> Refresh control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54106138A (en) * 1978-02-08 1979-08-20 Hitachi Ltd Memory refresh control system
JPS60696A (en) * 1983-06-16 1985-01-05 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory
JPH01227299A (en) * 1988-03-08 1989-09-11 Fujitsu Ltd Refresh control system for memory

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