JPS54160157A - Analog-digital converter - Google Patents

Analog-digital converter

Info

Publication number
JPS54160157A
JPS54160157A JP6896478A JP6896478A JPS54160157A JP S54160157 A JPS54160157 A JP S54160157A JP 6896478 A JP6896478 A JP 6896478A JP 6896478 A JP6896478 A JP 6896478A JP S54160157 A JPS54160157 A JP S54160157A
Authority
JP
Japan
Prior art keywords
input
integrated
time
integrator
saw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6896478A
Other languages
Japanese (ja)
Inventor
Daihachiro Tsuruno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6896478A priority Critical patent/JPS54160157A/en
Publication of JPS54160157A publication Critical patent/JPS54160157A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To ensure an A-D conversion with no overflow of the excessive input by integrating the integrated analog signals after swiching to the saw-tooth wave generator.
CONSTITUTION: The analog input signal is applied to integrator 1 via switch SW1 and then integrated for the prescribed time after reaching reference voltage V2 of comparator 2. Saw-tooth wave generator 7 featuring the opposite polarity to the input signal is actuated by the output of 1st gate 3 simultaneously with opening of SW1, and at the same time switch SW2 is closed via switch driving circuit 6. Thus, the discharging is continued until the output voltage of integrator 1 reaches voltage V2. This discharge time is equivalent to the square root of the integrated time and then counted 5 by the clock pulse via gate 4. Thus, the digital signal proportional to the input square root can be obtained. As a result, the A-D conversion becomes possible over a wide range from small input to large one.
COPYRIGHT: (C)1979,JPO&Japio
JP6896478A 1978-06-09 1978-06-09 Analog-digital converter Pending JPS54160157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6896478A JPS54160157A (en) 1978-06-09 1978-06-09 Analog-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6896478A JPS54160157A (en) 1978-06-09 1978-06-09 Analog-digital converter

Publications (1)

Publication Number Publication Date
JPS54160157A true JPS54160157A (en) 1979-12-18

Family

ID=13388862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6896478A Pending JPS54160157A (en) 1978-06-09 1978-06-09 Analog-digital converter

Country Status (1)

Country Link
JP (1) JPS54160157A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0391522A2 (en) * 1989-04-04 1990-10-10 Analogic Corporation C.T. data acquisition system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0391522A2 (en) * 1989-04-04 1990-10-10 Analogic Corporation C.T. data acquisition system

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