JPS54159138A - Priority processing system for buffer - Google Patents

Priority processing system for buffer

Info

Publication number
JPS54159138A
JPS54159138A JP6852878A JP6852878A JPS54159138A JP S54159138 A JPS54159138 A JP S54159138A JP 6852878 A JP6852878 A JP 6852878A JP 6852878 A JP6852878 A JP 6852878A JP S54159138 A JPS54159138 A JP S54159138A
Authority
JP
Japan
Prior art keywords
buffer
data
processing
circuit
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6852878A
Other languages
Japanese (ja)
Other versions
JPS6233619B2 (en
Inventor
Koji Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6852878A priority Critical patent/JPS54159138A/en
Publication of JPS54159138A publication Critical patent/JPS54159138A/en
Publication of JPS6233619B2 publication Critical patent/JPS6233619B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To enable the priority processing of data without providing the priority buffer, by storing the data of priority processing to the buffer after the end of processing for the buffer during readout, in the cyclic data processing of multi- stage buffer.
CONSTITUTION: The buffers M1 to MN of N-stage and the buffer counters A and B to control the cyclic operation are provided. The counter A indicates the number 9 of the buffer M to store the data of one unit formed from the data forming circuit K, the counter B indicates the number b of the buffer M read out from the data processing circuit P, and the numbers a and b are compared with each other at the comparison circuit C. When the data for emergency processing is taken place, the circuit K stores the data for emergency processing to the buffer when the circuit P is finished for processing for the data from the buffer during readout processing at present. The counter B makes the number b to -1, the buffer is again read out, the emergency data is processed with priority by the circuit P.
COPYRIGHT: (C)1979,JPO&Japio
JP6852878A 1978-06-07 1978-06-07 Priority processing system for buffer Granted JPS54159138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6852878A JPS54159138A (en) 1978-06-07 1978-06-07 Priority processing system for buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6852878A JPS54159138A (en) 1978-06-07 1978-06-07 Priority processing system for buffer

Publications (2)

Publication Number Publication Date
JPS54159138A true JPS54159138A (en) 1979-12-15
JPS6233619B2 JPS6233619B2 (en) 1987-07-22

Family

ID=13376311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6852878A Granted JPS54159138A (en) 1978-06-07 1978-06-07 Priority processing system for buffer

Country Status (1)

Country Link
JP (1) JPS54159138A (en)

Also Published As

Publication number Publication date
JPS6233619B2 (en) 1987-07-22

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