JPS54156457A - Automatic gain control circuit - Google Patents
Automatic gain control circuitInfo
- Publication number
- JPS54156457A JPS54156457A JP6513278A JP6513278A JPS54156457A JP S54156457 A JPS54156457 A JP S54156457A JP 6513278 A JP6513278 A JP 6513278A JP 6513278 A JP6513278 A JP 6513278A JP S54156457 A JPS54156457 A JP S54156457A
- Authority
- JP
- Japan
- Prior art keywords
- output
- converter
- conversion
- amplifier
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 abstract 4
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000005070 sampling Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To establish the AGC circuit effective to wired communication, by detecting the output of the variable gain amplifier, comparing and discriminating it with the reference signal level, and giving the signal in A/D conversion for the output to the set gain value of the amplifier with partial D/A conversion. CONSTITUTION:The input signal is amplified 2 via the variable gain amplifier 1, outputted and detected 3. The output of the detector 3 is compared and discriminated with the reference voltage A at the comparison circuit 4, and the error signal is DC-amplified 5 and converted into a digital value at the A/D converter 6. The partial D/A converter is provided in the converter 6, and analog signal value converted is fed to the variable gain amplifier 1 as the gain control value to control the gain. When the output of the comparison circuit 4 is stable, the A/D conversion of the converter 6 is stopped, the D/A conversion output is held constant at the sampling hold circuit to control the amplifier 1. Accordingly, if the transmission condition is once determined, since the setting of the reception gain is easily preset and it is stably held until the specified information communication is finished, it is effective to the facsimile communication.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6513278A JPS54156457A (en) | 1978-05-31 | 1978-05-31 | Automatic gain control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6513278A JPS54156457A (en) | 1978-05-31 | 1978-05-31 | Automatic gain control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54156457A true JPS54156457A (en) | 1979-12-10 |
Family
ID=13278033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6513278A Pending JPS54156457A (en) | 1978-05-31 | 1978-05-31 | Automatic gain control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54156457A (en) |
-
1978
- 1978-05-31 JP JP6513278A patent/JPS54156457A/en active Pending
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