JPS54152952A - A-d converter - Google Patents

A-d converter

Info

Publication number
JPS54152952A
JPS54152952A JP6251978A JP6251978A JPS54152952A JP S54152952 A JPS54152952 A JP S54152952A JP 6251978 A JP6251978 A JP 6251978A JP 6251978 A JP6251978 A JP 6251978A JP S54152952 A JPS54152952 A JP S54152952A
Authority
JP
Japan
Prior art keywords
signal
converter
circuit
analog
comparator circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6251978A
Other languages
Japanese (ja)
Inventor
Yasuhiro Kamikubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6251978A priority Critical patent/JPS54152952A/en
Publication of JPS54152952A publication Critical patent/JPS54152952A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To improve reliability by making it possible to detect easily an error signal in an A/D converter by providing the A/D converter, a D/A converter reciving its output, a delay circuit, and a comparator circuit.
CONSTITUTION: An analog input signal applied to terminal 1 is converted into a digital signal by A/D converter 5 and the signal is processed by date processor 17, whose output is supplied to terminal 18. To detect an error signal, the digital signals of converter 5 is reconverted by D/A converter into an analog signal, which is inputted to comparator circuit 21. After being delayed by delayed circuit 19 as much as the time equivalent to the sum of the conversion intervals of time of converters 5 and 20, the input analog signals is inputted to comparator circuit 21, where it is compared with the output signal of D/A 20. When the difference between both the analog signals compared by circuit 21 is above a fixed value, a detection signals is generated and outputted to device 17. On receiving the detection signal, device 17 outputs a signal which corresponds to the received signal, thereby making it possible to detect easily the occurrence of an error signal.
COPYRIGHT: (C)1979,JPO&Japio
JP6251978A 1978-05-24 1978-05-24 A-d converter Pending JPS54152952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6251978A JPS54152952A (en) 1978-05-24 1978-05-24 A-d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6251978A JPS54152952A (en) 1978-05-24 1978-05-24 A-d converter

Publications (1)

Publication Number Publication Date
JPS54152952A true JPS54152952A (en) 1979-12-01

Family

ID=13202504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6251978A Pending JPS54152952A (en) 1978-05-24 1978-05-24 A-d converter

Country Status (1)

Country Link
JP (1) JPS54152952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62286322A (en) * 1986-06-05 1987-12-12 Oki Electric Ind Co Ltd Data error detecting system by adpcm coding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62286322A (en) * 1986-06-05 1987-12-12 Oki Electric Ind Co Ltd Data error detecting system by adpcm coding

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