JPS54152775A - Monitor device of sequence controller - Google Patents

Monitor device of sequence controller

Info

Publication number
JPS54152775A
JPS54152775A JP6184978A JP6184978A JPS54152775A JP S54152775 A JPS54152775 A JP S54152775A JP 6184978 A JP6184978 A JP 6184978A JP 6184978 A JP6184978 A JP 6184978A JP S54152775 A JPS54152775 A JP S54152775A
Authority
JP
Japan
Prior art keywords
circuit
instruction
conditions
address
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6184978A
Other languages
Japanese (ja)
Inventor
Masayuki Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP6184978A priority Critical patent/JPS54152775A/en
Publication of JPS54152775A publication Critical patent/JPS54152775A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To identify as to whether or not a power flow PF under display is the true PF from a bus bar, by displaying the condutive conditions (The power flow PF) of a logical line, the use conditions of a stack and the ON-OFF conditions. CONSTITUTION:When the desired address is set by means of an address set means 8 and a reading indication means 9 is operated, sequence instructions corresponding to the address are read to an instruction reading circuit 10 from a program memory 11. The sequence instructions read are transmitted to a logical operation circuit 5 while being sent to a sequence instruction annunciator 3, and displayed at these portions. When an operation code STA among the sequence instructions is transferred to an instruction discriminating circuit 7, STA discriminating control signals are drawn from the circuit 7, and the contents of a counter 6 are altered. Thus, all display portions L0-L3 of a stack annunciator 1 are put out, and the computing results of the logical operation circuit 5 are displayed to a power-flow display portion 4.
JP6184978A 1978-05-23 1978-05-23 Monitor device of sequence controller Pending JPS54152775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6184978A JPS54152775A (en) 1978-05-23 1978-05-23 Monitor device of sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6184978A JPS54152775A (en) 1978-05-23 1978-05-23 Monitor device of sequence controller

Publications (1)

Publication Number Publication Date
JPS54152775A true JPS54152775A (en) 1979-12-01

Family

ID=13182944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6184978A Pending JPS54152775A (en) 1978-05-23 1978-05-23 Monitor device of sequence controller

Country Status (1)

Country Link
JP (1) JPS54152775A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989010586A1 (en) * 1988-04-22 1989-11-02 Fanuc Ltd Program display system of a pc

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989010586A1 (en) * 1988-04-22 1989-11-02 Fanuc Ltd Program display system of a pc

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