JPS54142026A - Memory circuit - Google Patents

Abstract

PURPOSE:To secure the same phase level for the data output as the writing data by using the input data signals and the writing timing which is activated only in the early writing cycle. CONSTITUTION:In the case of the early write cycle, node 5 and 6 are discharged by rising of the early write signal EW and changes into the earth potential. Thus, no information is tansmitted from the memory cell. With increment of timing OE, the voltage of node 2 rises almost in synchronization with OE through conducting MOSFETQ4. While node 3 is discharged with nonconducting MOSFETQ6 and Q7, and node 4 is kept at a dynamic low level regardless of increment of OE but changed to the earth potential via MOSFETQ14 with rising of node 2. As a result, MOSFETQ17 conducts with Q18 turned nonconductive, thus a high level emerging at output DATAOUT. So is with DATAIN at a low level. Thus, such function can be obtained as to produce the same phase level at DATAOUT as the writing data.