JPS54140433A - Data processor - Google Patents

Data processor

Info

Publication number
JPS54140433A
JPS54140433A JP4789278A JP4789278A JPS54140433A JP S54140433 A JPS54140433 A JP S54140433A JP 4789278 A JP4789278 A JP 4789278A JP 4789278 A JP4789278 A JP 4789278A JP S54140433 A JPS54140433 A JP S54140433A
Authority
JP
Japan
Prior art keywords
slicer
unit
mixer
control unit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4789278A
Other languages
Japanese (ja)
Inventor
Masayuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4789278A priority Critical patent/JPS54140433A/en
Publication of JPS54140433A publication Critical patent/JPS54140433A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To secure the use of the bus structure limited physically through the logical multiplication by using the multi-value logic circuit for the signal line for memory driving.
CONSTITUTION: Main memory 1 is shared by arithmetic control unit 2 and input/ output device 3, and mixer 5, bus line 4 and slicer 6 are provided between unit 2 and device 3. Mixer 5 converts the supplied parallel and binary digital information into one multi-value signal which is transferred to slicer 6 through bus line 4. Slicer 6 returns the multi-value signal to the original binary digital information and then applies the information to memory block control unit 7. As a result, the simultaneous and parallel access can be given to the different blocks of main memory 1 from unit 2 and device 3.
COPYRIGHT: (C)1979,JPO&Japio
JP4789278A 1978-04-24 1978-04-24 Data processor Pending JPS54140433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4789278A JPS54140433A (en) 1978-04-24 1978-04-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4789278A JPS54140433A (en) 1978-04-24 1978-04-24 Data processor

Publications (1)

Publication Number Publication Date
JPS54140433A true JPS54140433A (en) 1979-10-31

Family

ID=12788049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4789278A Pending JPS54140433A (en) 1978-04-24 1978-04-24 Data processor

Country Status (1)

Country Link
JP (1) JPS54140433A (en)

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