JPS54138328A - Television tuner - Google Patents

Television tuner

Info

Publication number
JPS54138328A
JPS54138328A JP4585578A JP4585578A JPS54138328A JP S54138328 A JPS54138328 A JP S54138328A JP 4585578 A JP4585578 A JP 4585578A JP 4585578 A JP4585578 A JP 4585578A JP S54138328 A JPS54138328 A JP S54138328A
Authority
JP
Japan
Prior art keywords
circuit
signal
balanced
output
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4585578A
Other languages
Japanese (ja)
Inventor
Shigeo Fujimori
Kenichi Torii
Shoichi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4585578A priority Critical patent/JPS54138328A/en
Publication of JPS54138328A publication Critical patent/JPS54138328A/en
Pending legal-status Critical Current

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Landscapes

  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE: To enable to perform balanced output of input signal without effect of noise for the input signal, by receiving the signal of the dual tuning circuit between stages as being balanced at the mixer circuit, and picking up the balanced output with input and mixing of the oscillation signal from the local oscillation circuit.
CONSTITUTION: The dual tuning circuit 32 between stages is constituted that it selects the specified frequency signal from the high frequency signal fed to the primary side and picks up as the balanced output at the secondary side, and the output of the circuit 32 is fed to the terminals 47 and 48 as being balanced. On the other hand, the local oscillation signal is fed to the terminals 50 and 51, those two input signals are mixed at the mixer circuit 33 and balanced output is picked up from the output terminals 52 and 54 to feed the local oscillation signal from the local oscillation circuit 34 to the mixer circuit. Thus, without deterioration of noise index, the input signal is fed to the mixer circuit 33 to pick up the balanced output.
COPYRIGHT: (C)1979,JPO&Japio
JP4585578A 1978-04-20 1978-04-20 Television tuner Pending JPS54138328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4585578A JPS54138328A (en) 1978-04-20 1978-04-20 Television tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4585578A JPS54138328A (en) 1978-04-20 1978-04-20 Television tuner

Publications (1)

Publication Number Publication Date
JPS54138328A true JPS54138328A (en) 1979-10-26

Family

ID=12730814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4585578A Pending JPS54138328A (en) 1978-04-20 1978-04-20 Television tuner

Country Status (1)

Country Link
JP (1) JPS54138328A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103543A (en) * 1980-01-21 1981-08-18 Toshiba Corp Tuner circuit of television picture receiver
JPH01276930A (en) * 1988-04-28 1989-11-07 Matsushita Electric Ind Co Ltd Electronic tuner

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103543A (en) * 1980-01-21 1981-08-18 Toshiba Corp Tuner circuit of television picture receiver
JPS6221456B2 (en) * 1980-01-21 1987-05-13 Tokyo Shibaura Electric Co
JPH01276930A (en) * 1988-04-28 1989-11-07 Matsushita Electric Ind Co Ltd Electronic tuner

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