JPS54135315A - Power source stabilizing system - Google Patents

Power source stabilizing system

Info

Publication number
JPS54135315A
JPS54135315A JP4298978A JP4298978A JPS54135315A JP S54135315 A JPS54135315 A JP S54135315A JP 4298978 A JP4298978 A JP 4298978A JP 4298978 A JP4298978 A JP 4298978A JP S54135315 A JPS54135315 A JP S54135315A
Authority
JP
Japan
Prior art keywords
circuit
output
detecting
fed
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4298978A
Other languages
Japanese (ja)
Inventor
Mitsuo Nakamura
Nobuhisa Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4298978A priority Critical patent/JPS54135315A/en
Publication of JPS54135315A publication Critical patent/JPS54135315A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve efficiency, by successively detecting the fluctuation portions of the voltage of each output circuit in time sharing when the secondary side is provided with a plurality of output circuits, and by stabilizing a power source by controlling an inverter circuit at the primary side by the detecting signals.
CONSTITUTION: When the output of an inverter circuit 2 is fed to a plurality of load through a transformer 3, a frequency dividing circuit 10 is mounted to an oscillation circuit 5, and switching means S1∼S3 are operated in order every three periods of output pulses from the oscillation circuit 5. Consequently, when the switch S1 operates, a rectifying circuit 7 at the secondary side of the transformer and a smoothing circuit 8 are connected by a contact S11, and power is fed while the signals of a detecting circuit 6 are fed back to a control circuit 4 through a contact S12, thus stabilizing output. As a result, the loss of power is decreased and efficiency can be improved because the switches S1∼S3 successively function, the inverter circuit is controlled in time sharing and each circuit is stabilized.
COPYRIGHT: (C)1979,JPO&Japio
JP4298978A 1978-04-12 1978-04-12 Power source stabilizing system Pending JPS54135315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4298978A JPS54135315A (en) 1978-04-12 1978-04-12 Power source stabilizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4298978A JPS54135315A (en) 1978-04-12 1978-04-12 Power source stabilizing system

Publications (1)

Publication Number Publication Date
JPS54135315A true JPS54135315A (en) 1979-10-20

Family

ID=12651431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4298978A Pending JPS54135315A (en) 1978-04-12 1978-04-12 Power source stabilizing system

Country Status (1)

Country Link
JP (1) JPS54135315A (en)

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