JPS54134522A - Read circuit of memory - Google Patents

Read circuit of memory

Info

Publication number
JPS54134522A
JPS54134522A JP4365178A JP4365178A JPS54134522A JP S54134522 A JPS54134522 A JP S54134522A JP 4365178 A JP4365178 A JP 4365178A JP 4365178 A JP4365178 A JP 4365178A JP S54134522 A JPS54134522 A JP S54134522A
Authority
JP
Japan
Prior art keywords
output
gate voltage
voltage
integrator
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4365178A
Other languages
Japanese (ja)
Inventor
Yoshinosuke Nagata
Kazuyoshi Tsukamoto
Hiroshi Kutsuyama
Terutoshi Sasami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4365178A priority Critical patent/JPS54134522A/en
Publication of JPS54134522A publication Critical patent/JPS54134522A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Abstract

PURPOSE:To reduce drift without requiring the special amplification of the read output by reading out the gate voltage, where the drain current becomes constant, and making this gate voltage of the output. CONSTITUTION:MOS FET 1 which is a memory reads out the gate voltage, where the drain current becomes constant, and makes this gate voltage of the output. While the output of converter 3 to comparator 4 and refrence voltage Vref do not agree with each other, the output of comparator 4 is integrated by integrator 5, and the output of integrator 5 is applied to the gate of FET 1. Therefore, the gate voltage is changed, and the source current is changed correspondingly. When the source current becomes a prescribed value and the output voltage of converter 3 and the reference voltage agree with each other, the output of comparator 4 becomes zero, and the output of integrator 5 reaches balance at this point and becomes the read output of FET 1.
JP4365178A 1978-04-10 1978-04-10 Read circuit of memory Pending JPS54134522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4365178A JPS54134522A (en) 1978-04-10 1978-04-10 Read circuit of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4365178A JPS54134522A (en) 1978-04-10 1978-04-10 Read circuit of memory

Publications (1)

Publication Number Publication Date
JPS54134522A true JPS54134522A (en) 1979-10-19

Family

ID=12669761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4365178A Pending JPS54134522A (en) 1978-04-10 1978-04-10 Read circuit of memory

Country Status (1)

Country Link
JP (1) JPS54134522A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04238196A (en) * 1991-01-22 1992-08-26 Nec Ic Microcomput Syst Ltd Eprom circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04238196A (en) * 1991-01-22 1992-08-26 Nec Ic Microcomput Syst Ltd Eprom circuit

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